The FT 5000 Smart Transceiver is our FT 5000 Smart next-generation chip for smart networks. Transceiver FT-X3 Communications It is the key product in the LONWORKS Transformer 2.0 platform the next generation of The Next-generation LONWORKS products designed to greatly Free Topology Smart Transceiver increase the power and capability of LONWORKS enabled devices, while lowering development and node costs. The FT 5000 Smart Transceiver integrates a high-performance Neuron Core with a free topology twisted-pair transceiver. Combined with the new low-cost FT-X3 Communications Transformer and inexpensive serial memory, the FT 5000 Smart Transceiver provides a lower-cost, higher-performance LONWORKS solution than previous-generation FT Smart Transceivers. FEATURES 3.3V operation. Unique 48-bit Neuron ID in every device The FT 5000 Smart Transceiver for network installation and management. supports polarity-insensitive cabling Higher-performance Neuron Core using a star, bus, daisy-chain, loop, or internal system clock scales up Very high common-mode noise immunity. combination topology (see Figure 2). to 80MHz. -40C to +85C operating tempera- Thus, installers dont have to follow a Substantial device price reduction. ture range. strict set of wiring rules imposed by other Serial memory interface for networking technologies. Instead, they DESCRIPTION inexpensive external EEPROM can install wiring in the fastest and most The FT 5000 Smart Transceiver includes and afl sh non -volatile memorie s. cost-effective manner, thereby saving three independent 8-bit logical processors time and money. Free topology wiring Supports up to 254 Network to manage the physical MAC layer, the also simplifie s net work expansion by Variables (NVs) and 127 aliases. network, and the user application. These eliminating restrictions on wire routing, Low-cost surface mount FT-X3 are called the Media-Access Control splicing, and device placement. Communications Transformer. (MAC) processor, the network (NET) User-programmable interrupts provide processor, and the application (APP) faster response time to external events. processor, respectively (see Figure 1). At higher system clock rates, there is also a Includes hardware UART with 16-byte Singly-Terminated Bus Topology fourth processor to handle interrupts. receive and transmit FIFOs. Star Topology 7 mm x 7 mm 48-pin QFN package. 2 Doubly-Terminated Bus Topology 12 Comm External / I / O / Supports polarity-insensitive free Port Transformer topology star, daisy chain, bus, loop, 2-6 Serial NVM 2 / Memory (SPI or I C) IRQ CPU Interface or mixed topology wiring. Compliant with TP/FT-10 channels APP CPU Free Topology RAM using FT 3120 /FT 3150 Smart (64K x 8) Loop Topology Transceivers and FTT-10/FTT-10A/ = FT device NET CPU = Terminatior LPT-10/LPT-11 Transceivers. ROM (16K x 8) MAC CPU 12 I/O pins with 35 programmable Figure 2: Free Topology Network Congfi urations standard I/O models. Clock, Reset, JTAG and Service The FT-X3 Communications Transformer is Supports up to 42KB of application 5 a surface mount communications trans- code space. former thats compatible with both the FT 64KB RAM (44KB user-accessible) Figure 1: FT 5000 Smart Transceiver Chip 5000 Smart Transceiver and the previous- and 16KB ROM on-chip memories. 1 XIN XOUT RST~ SVC~generation FT 3120/FT 3150 Smart running with an 80MHz internal system I/O Pins and Counters Transceivers. The FT-X3 Communications clock is thus 16 times faster than a The FT 5000 Smart Transceiver provides Transformer provides equivalent noise 10MHz Neuron 3120/3150 Core running. 12 bidirectional I/O pins that are immunity to both the FT-X1 and FT-X2 5V-tolerant and can be configured to The 5MHz internal system clock mode in Communication Transformers, the operate in one or more of 35 predenfi ed the FT 5000 Smart Transceiver provides previous-generation communication trans- standard input/output models. The chip backward compatibility to support formers. However, the FT-X3 Communica- also has two 16-bit timer/counters that timing-critical applications designed tions Transformer is not pin-compatible reduce the need for external logic and for the 10MHz FT 3150 or FT 3120 with the FT-X2 Communication Transform- software development. Smart Transceiver. er (which is also a surface mount trans- Memory Architecture The Neuron Core inside the FT 5000 former). The FT 5000 Smart Transceiver The FT 5000 Smart Transceiver uses Smart Transceiver includes a built- can also be used with the FT-X1 and FT-X2 inexpensive external serial EEPROM and in hardware multiplier and divider to Communication Transformers. afl sh memories for non-volatile application increase the performance of arithmetic Backward Compatibility and data storage, and optionally for future operations. The FT 5000 Smart Transceiver is fully Neuron rfi mware upgrades. It has 16KB Support for more network variables. compliant with the TP/FT-10 channel of ROM and 64KB (44KB user-accessible) Because it use s Neuron rfi mware ver sion and can communicate with devices of RAM on the chip. It has no on-chip 19, the F T 5000 Smar t Transceiver that use Echelons FTT-10/FTT-10A non-volatile memor y (EEPROM or afl sh) supports applications with up to 254 Transceivers, FT 3120/FT 3150 Smart for application use. Each chip, however, network variables and 127 aliases for Transceivers, or LPT-10/LPT-11 Link contains its unique Neuron identifier Neuron hosted devices (devices without Power Transceivers. (Neuron ID) in an on-chip, non-volatile, a host microprocessor). A Series 3100 read-only memory. The Neuron Core in the FT 5000 Smart Neuron Chip or Smart Transceiver with Transceiver uses the same instruction The application code and configuration Neuron rfi mware ver sion 15 or earlier set and architecture as the previous- data are stored in the external non-volatile supports up to 62 network variables and generation Neuron Core, with two new memory (NVM) and copied into the internal 62 aliases for Neuron hosted devices. additional instructions for hardware RAM during device reset the instructions Series 3100 chips with Neuron rfi mware multiplication and division. The Series then execute from internal RAM. Writes version 16 or later support up to 254 5000 Neuron Core is source code to NVM are shadowed in the internal network variables. You must use the compatible with applications written RAM and pushed out to external NVM by NodeBuilder FX Development Tool to take for the Series 3100 Neuron Core. the Neuron rfi mware (see Figure 2). The advantage of 254 network variables. Applications written for the Series application does not manage NVM directly. Interrupts. The FT 5000 Smart Transceiver 3100 Neuron Core must be recompiled External memories supported. The FT lets developers denfi e application with the NodeBuilder FX Development 5000 Smart Transceiver supports two interrupts to handle asynchronous events Tool or the Mini FX Evaluation Kit before serial interfaces for accessing off-chip, triggered by selected state changes on any they can be used with the FT 5000 non-volatile memories: serial Inter- of the 12 I/O pins, by on-chip hardware Smart Transceiver. Integrated Circuit (I2C) and serial peripheral timer-counter units, or by an on-chip high- The FT 5000 Smart Transceiver uses inter face (SPI). EEPROM and afl sh memor y performance hardware system timer. An Neuron rfi mware ver sion 19. Firmware devices can use either the I2C interface or application uses the Neuron C interrupt() ver sions prior to ver sion 19 are not the SPI interface. However, at the time of clause to denfi e the interrupt condition compatible with the FT 5000 Smart publication, there are no serial afl sh par ts and the interrupt task that handles the Transceiver. The Neuron rfi mware is that use the I2C protocol and meet the condition. The Neuron C program runs pre-programmed into the on-chip ROM. required specicfi ations for the Series 5000 the interrupt task whenever the interrupt The FT 5000 Smart Transceiver can also external memory interface. condition is met. See the Neuron C be configured to read newer rfi mware Programmers Guide for more information Ex ternal serial EEPROMs and afl sh from external memories, allowing the about writing interrupt tasks and handling devices, which are inexpensive and come rfi mware to be upgraded over time. interrupts. in very small form factors, are available Enhanced Performance from multiple vendors. JTAG. The FT 5000 Smart Transceiver Faster system clock. The internal system provides an interface for the Institute of The FT 5000 Smart Transceiver requires clock for the FT 5000 Smart Transceiver Electrical and Electronics Engineers (IEEE) at least 2KB of off-chip memory available c an be user- configured to run from 5MHz Standard Test Access Port and Boundary- in an EEPROM device to store the to 80MHz. The required external crystal Scan Architecture (IEEE 1149.1-1990) configuration data. The application code provides a 10MHz clock frequency, and of the Joint Test Action Group (JTAG) to can be stored either in the EEPROM (by an internal PLL boosts the frequency to allow a Series 5000 chip to be included using a larger-capacity EEPROM device) or a maximum of 80MHz as the internal in the boundary-scan chain for device in a afl sh memor y device used in addition system clock speed. The previous- production tests. A Boundary Scan to the 2KB (minimum) EEPROM. Thus, the generation Neuron 3120/3150 Core Description Language (BSDL) lfi e for external memory for the FT 5000 Smart divided the external oscillator frequency the FT 5000 Smart Transceiver can be Transceiver has one of the configurations by two to create the internal system downloaded from Echelons Web site. listed in Table 1: clock. An FT 5000 Smart Transceiver 2