Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY8CPLC20 Datasheet Powerline Communication Solution owerline Communication Solution Up to four full duplex UARTs Features Multiple SPI masters or slaves Powerline communication solution Connectable to all GPIO Pins Integrated powerline modem PHY Complex peripherals by combining blocks Frequency shift keying modulation Flexible on-chip memory Configurable baud rates up to 2400 bps 32 KB flash program storage 50,000 erase or write cycles Powerline optimized network protocol 2 KB SRAM data storage Integrates data link, transport, and network layers EEPROM emulation in flash Supports bidirectional half duplex communication Programmable pin configurations 8-bit CRC error detection to minimize data loss 2 25 mA sink, 10 mA source on all GPIOs I C enabled powerline application layer 2 Pull-up, Pull-down, high Z, strong, or open drain drive Modes Supports I C frequencies of 50, 100, and 400 kHz on all GPIO Reference designs for 110 V/240 V AC and 12 V/24 V AC/DC Up to 12 analog inputs on all GPIOs Powerlines Configurable interrupt on all GPIOs Reference designs comply with CENELEC EN 50065-1:2001 and FCC Part 15 Additional system resources 2 Powerful Harvard-architecture Processor I C slave, master, and multi-master to 400 kHz M8C processor speeds to 24 MHz Watchdog and sleep timers Two 8x8 multiply, 32-bit accumulate User-configurable low-voltage detection Integrated supervisory circuit Programmable system resources (PSoC Blocks) On-chip precision voltage reference 12 Rail-to-Rail Analog PSoC Blocks provide: Up to 14-bit ADCs Complete development tools Up to 9-bit DACs Free development software (PSoC Designer) Programmable gain amplifiers Full-featured in-circuit emulator (ICE) and programmer Full-speed emulation Programmable filters and comparators Complex breakpoint structure 16 Digital PSoC Blocks provide: 128 KB trace memory 8 to 32-bit Timers, Counters, and PWMs Complex events CRC and PRS Modules C Compilers, assembler, and linker Logic Block Diagram Powerline Communication Solution Embedded Application Powerline Network Programmable Protocol System Resources Digital and Analog Peripherals Additional System Physical Layer FSK Resources Modem MAC, Decimator, I2C, SPI, UART etc. PLC Core PSoC Core Powerline Transceiver Packet AC/DC Powerline Coupling Circuit (110V/240V AC, 12V/24V AC/DC etc.) Powerline Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-48325 Rev. *O Revised October 5, 2018 CY8CPLC20