Combined with inexpensive serial Neuron 5000 memory, the Neuron 5000 Processor Processor provides a lower-cost, higher-performance The Next-generation Neuron Chip for LONWORKS solution than those based on LONWORKS Control previous-generation Neuron 3120 and Networks Neuron 3150 chips. The Neuron 5000 Processor incorporates communication and control functions on a single chip, in both hardware and firmware, to facilitate the design of a LONWORKS device. Its flexible 5-pin communications port can be congfi ured to interface with a wide variety of media transceivers including twisted-pair, RF, IR, fiber-optics, and coaxial at a wide range of data rates. FEATURES DESCRIPTION 3.3V operation. The Neuron 5000 Processor includes Backward Compatibility 3 independent 8-bit logical processors The pins for the Neuron 5000 Higher-performance Neuron Core to manage the physical MAC layer, the Processors communications port drive internal system clock scales up network, and the user application. These a 3.3V signal and are 5V input-tolerant. to 80 MHz. are called the Media-Access Control Thus, the Neuron 5000 Processor is Enables lower-cost device designs. (MAC) processor, the network (NET) compatible with 3.3V transceivers and Serial memory interface for processor, and the application (APP) with 5V transceivers that have TTL- inexpensive external EEPROM processor, respectively (see Figure 1). At compatible input. and flash non-volatile memories. higher system clock rates, there is also a The Neuron 5000 Processor is fourth processor to handle interrupts. Supports up to 254 Network Variables compatible with TP/XF-1250 and EIA- (NVs) and 127 aliases. 485 channels, and can be used with the 5 12 Comm User programmable interrupts provide External / I / O / Lno Wskro LPT-11 Link Power Transceiver. Port Transformer faster response time to external events. It also supports a variety of other 2-6 Serial NVM 2 / Memory (SPI or I C) IRQ CPU Interface channels used with previous-generation Includes hardware UART with 16-byte Neuron Chips, such as RF, IR, fiber-optic, receive and transmit FIFOs. APP CPU and coaxial. It does not, however, support RAM 7mm x 7mm 48-pin QFN package. (64K x 8) a TP/XF-78 channel. To support a TP/FT- 5-pin network communications port NET CPU 10 channel, use an Echelon Free Topology with 3.3V drive and 5V-tolerant pins. Smart Transceiver (FT 5000 Smart ROM (16K x 8) MAC CPU 12 I/O pins with 35 programmable Transceiver) to support a PL-20 power standard I/O models. line channel, use an Echelon Power Line Clock, Reset, JTAG and Service Smart Transceiver (PL 3120/3150/3170 Supports up to 42KB of application 5 Smart Transceiver). Echelons Smart code space. Transceivers integrate the transceiver for 64KB RAM (44KB user accessible) Figure 1: Neuron 5000 Processor the channel type and the Neuron Core and 16KB ROM on-chip memories. into a single chip, which enables smaller Unique 48-bit Neuron ID in every designs and provides cost savings. device for network installation and The Neuron Core in the Neuron 5000 management. Processor uses the same instruction -40C to +85C operating set and architecture as the previous- temperature range. generation Neuron Core, with 2 new additional instructions for hardware 1 XIN XOUT RST~ SVC~multiplication and division. The Series Series 3100 chips with Neuron firmware must be redesigned for a Neuron 5000 5000 Neuron Core is source code version 16 or later support up to 254 Processor to use Single-Ended Mode with compatible with applications written network variables. You must use the external circuitry to provide Single-Ended for the Series 3100 Neuron Core. NodeBuilder FX Development Tool to take to Differential Mode conversions. See Applications written for the Series 3100 advantage of 254 network variables. the Series 5000 Chip Data Book and the Neuron Core must be recompiled with the Connecting a Neuron 5000 Processor Interrupts. The Neuron 5000 Processor NodeBuilder FX Development Tool or the to an External Transceiver Engineering lets developers denfi e application Mini FX Evaluation Kit before they can be Bulletin for more information. interrupts to handle asynchronous used with the Neuron 5000 Processor. events triggered by selected state Any 3.3V transceiver or a 5V transceiver The Neuron 5000 Processor uses Neuron changes on any of the 12 I/O pins, by with TTL-compatible inputs can be rfi mware version 19. Firmware versions on-chip hardware timer-counter units, used with the Neuron 5000 Processor prior to version 19 are not compatible or by an on-chip high-performance because the communications port has with the Neuron 5000 Processor. The hardware system timer. An application pins that are 5V tolerant and drive a Neuron firmware is pre-programmed uses the Neuron C interrupt() clause to 3.3V signal. Common transceiver types into the on-chip ROM. The Neuron 5000 denfi e the interrupt condition and the that can be used with a Neuron 5000 Processor can also be configured to read interrupt task that handles the condition. Processor include twisted-pair, RF, IR, newer firmware from external memories, The Neuron C program runs the interrupt bfi er-optic, and coaxial. allowing the firmware to be upgraded task whenever the interrupt condition is I/O Pins and Counters over time. met. See the Neuron C Programmers The Neuron 5000 Processor provides Guide for more information about writing Enhanced Performance 12 bidirectional I/O pins that are 5V interrupt tasks and handling interrupts. Faster system clock. The internal system tolerant and can be configured to clock for the Neuron 5000 Processor JTAG. The Neuron 5000 Processor operate in one or more of 35 predenfi ed can be user-configured to run from 5MHz provides an interface for the Institute standard input/output models. The chip to 80MHz. The required external crystal of Electrical and Electronics Engineers also has two 16-bit timer/counters that provides a 10MHz clock frequency, and (IEEE) Standard Test Access Port and reduce the need for external logic and an internal PLL boosts the frequency to Boundary-Scan Architecture (IEEE 1149.1- software development. a maximum of 80MHz as the internal 1990) of the Joint Test Action Group Memory Architecture system clock speed. The previous- (JTAG) to allow a Series 5000 chip to The Neuron 5000 Processor uses generation Neuron 3120/3150 Core be included in the boundary-scan chain inexpensive external serial EEPROM divided the external oscillator frequency for device production tests. A Boundary and flash memories for non-volatile by two to create the internal system clock. Scan Description Language (BSDL) file application and data storage, and Hence, a Neuron 3120/3150 Core running for the Neuron 5000 Processor can be optionally for future Neuron firmware with a 10MHz external crystal had a 5MHz downloaded from Echelons Web site. upgrades. It has 16KB of ROM and internal system clock. A Neuron 5000 Communications Port 64KB (44 KB user-accessible) of RAM Processor running with an 80MHz internal The Neuron 5000 Processor includes on the chip. It has no on-chip non- clock is thus 16 times faster than a 10MHz a versatile 5-pin communications port volatile memory (EEPROM or flash) for Neuron 3120/3150 Core running with a that can be configured in two ways: 3.3 application use. Each chip, however, 5MHz internal system clock. V Single-Ended Mode and 3.3 V Special- contains its unique Neuron identifier The 5MHz system clock mode in the Purpose Mode. In Single-Ended Mode, (Neuron ID) in an on-chip, non-volatile, Neuron 5000 Processor provides backward pin CP0 is used for receiving serial data, read-only memory. compatibility to support time-critical pin CP1 for transmitting serial data, The application code and configuration applications designed for the 10MHz and pin CP2 for enabling an external data are stored in the external non-volatile Neuron 3150 or Neuron 3120 processor. transmitter. Data is communicated using memory (NVM) and copied into the internal Differential Manchester encoding. The Neuron Core inside the Neuron 5000 RAM during device reset the instructions Processor includes a built-in hardware In Special-Purpose Mode, pin CP0 is then execute from internal RAM. Writes multiplier and divider to increase the used for receiving serial data, pin CP1 for to NVM are shadowed in the internal performance of arithmetic operations. transmitting serial data, pin CP2 transmits RAM and pushed out to external NVM by a bit clock, and pin CP4 transmits a frame the Neuron firmware (see Figure 1). The Support for more network variables. clock for use by an external intelligent application does manage NVM directly. Because it uses Neuron system firmware transceiver. In this mode, the external Version 19, the Neuron 5000 Processor External memories supported. The Neuron transceiver is responsible for encoding supports applications with up to 254 5000 Processor supports two serial and decoding the data stream. network variables and 127 aliases for interfaces for accessing off-chip non- Neuron hosted devices (devices without Unlike the Neuron 3120/3150 Chips, volatile memories: serial Inter-Integrated 2 a host microprocessor). A Series 3100 the Neuron 5000 Processor does Circuit (I C) and serial peripheral interface Neuron Chip or Smart Transceiver with not support the Differential Mode (SPI). EEPROM and flash memory devices 2 Neuron firmware Version 15 or earlier configuration for the communications can use either the I C interface or the SPI supports up to 62 network variables and port. Thus, devices that require interface flash memory devices must use 62 aliases for Neuron hosted devices. Differential Mode transceiver types the SPI interface. 2