AT25DF011
1-Mbit, 1.65V Minimum
SPI Serial Flash Memory with Dual-Read Support
PRELIMINARY DATASHEET
Features
Single 1.65V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (t ) of 6 ns
V
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.5ms Typical Page Program (256 Bytes) Time
50ms Typical 4-Kbyte Block Erase Time
350ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
200nA Ultra Deep Power Down current (Typical)
5A Deep Power-Down Current (Typical)
25uA Standby current (Typical)
4.5mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Temperature Range:-10C to +85C (1.65V to 3.6V), -40C to +85 (1.7V to 3.6V)
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6 mm)
8-lead TSSOP Package
DS-25DF011032C2/20151. Description
The Adesto AT25DF011 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer
based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25DF011, with its page erase granularity it is ideal for data storage as well, eliminating the
need for additional data storage devices.
The erase block sizes of the AT25DF011 have been optimized to meet the needs of today's code and data storage applications.
By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules
and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that
occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space
efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device
density.
The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as
unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in many different systems, the AT25DF011 supports read, program, and erase operations with a
wide supply voltage range of 1.65V to 3.6V. No separate voltage is required for programming and erasing.
2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Asserted
Symbol Name and Function State Type
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down
mode), and the SO pin will be in a high-impedance state. When the device is deselected, data
will not be accepted on the SI pin.
CS Low Input
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation such as
a program or erase cycle, the device will not enter the standby mode until the completion of the
operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow
of data to and from the device. Command, address, and input data present on the SI pin is
SCK - Input
always latched in on the rising edge of SCK, while output data on the SO pin is always clocked
out on the falling edge of SCK.
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data
input including command and address sequences. Data on the SI pin is always latched in on the
rising edge of SCK.
With the Dual-Output Read commands, the SI Pin becomes an output pin (I/O ) in conjunction
0 Input/
SI (I/O ) -
0
with other pins to allow two bits of data on (I/O ) to be clocked out on every falling edge of SCK.
1-0 Output
To maintain consistency with the SPI nomenclature, the SI (I/O ) pin will be referenced as the SI
0
pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O
0.
Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).
AT25DF011 2
DS-25DF011032C2/2015