X-On Electronics has gained recognition as a prominent supplier of AT25SF041-SHDHR-T NOR Flash across the USA, India, Europe, Australia, and various other global locations. AT25SF041-SHDHR-T NOR Flash are a product manufactured by Dialog Semiconductor. We provide cost-effective solutions for NOR Flash, ensuring timely deliveries around the world.

AT25SF041-SHDHR-T Dialog Semiconductor

AT25SF041-SHDHR-T electronic component of Dialog Semiconductor
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See Product Specifications
Part No.AT25SF041-SHDHR-T
Manufacturer: Dialog Semiconductor
Category: NOR Flash
Description: NOR Flash 4 Mbit, 3.0V (2.5V to 3.6V), -40C to 125C, SOIC-W 208mil (Tape & Reel), Single, Dual, Quad SPI NOR flash
Datasheet: AT25SF041-SHDHR-T Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
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Obsolete
Availability Price Quantity
0
MOQ : 1
Multiples : 1
1 : USD 1.5879
10 : USD 0.7492
100 : USD 0.4858
N/A

Obsolete
   
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We are delighted to provide the AT25SF041-SHDHR-T from our NOR Flash category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the AT25SF041-SHDHR-T and other electronic components in the NOR Flash category and beyond.

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AT25SF041 4-Mbit, 2.5V Minimum SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support Features Single 2.5V - 3.6V Supply Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 and 3 Supports Dual and Quad Output Read 104MHz Maximum Operating Frequency Clock-to-Output (t ) of 6 ns V Flexible, Optimized Erase Architecture for Code + Data Storage Applications Uniform 4-Kbyte Block Erase Uniform 32-Kbyte Block Erase Uniform 64-Kbyte Block Erase Full Chip Erase Hardware Controlled Locking of Protected Blocks via WP Pin 3 Protected Programmable Security Register Pages Flexible Programming Byte/Page Program (1 to 256 Bytes) Fast Program and Erase Times 0.7ms Typical Page Program (256 Bytes) Time 70ms Typical 4-Kbyte Block Erase Time 300ms Typical 32-Kbyte Block Erase Time 600ms Typical 64-Kbyte Block Erase Time JEDEC Standard Manufacturer and Device ID Read Methodology Low Power Dissipation 2A Deep Power-Down Current (Typical) 10A Standby current (Typical) 4mA Active Read Current (Typical) Endurance: 100,000 Program/Erase Cycles Data Retention: 20 Years Complies with Full Industrial Temperature Range Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options 8-lead SOIC (150-mil and 208-mil) 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm and 2 x 3 x 0.6 mm) 8-lead TSSOP (4 x 4 mm) Die in Wafer Form DS-25SF041044F4/2016Description The Adesto AT25SF041 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25SF041 is ideal for data storage as well, eliminating the need for additional data storage devices. The erase block sizes of the AT25SF041 have been optimized to meet the needs of today s code and data storage applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. The device also contains three pages of Security Register that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register pages can be individually locked. 1. Pin Descriptions and Pinouts Table 1-1. Pin Descriptions Asserted Symbol Name and Function State Type CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. CS Low Input A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin SCK - Input is always latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched in on the rising edge of SCK. With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output pin (I/O ) in conjunction with other pins to allow two or four bits of data on (I/O ) to be clocked 0 3-0 in on every falling edge of SCK SI (I/O ) - Input/Output 0 To maintain consistency with the SPI nomenclature, the SI (I/O ) pin will be referenced as 0 the SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it will be referenced as I/O 0 Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted). AT25SF041 2 DS-25SF041044F4/2016

Tariff Desc

8542.32.00 32 No ..CMOS and MOS Read Only Memory and Programmable Read Only Memory whether erasable or non-erasable (for example, flash memory, EPROM, E2PROM, EAPROM, NOVRAM, ROM and PROM)
Adesto Technologies
Dialog Semiconductor GmbH
DLG
Echelon / Adesto
Echelon Corporation
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