Features Single 2.7V - 3.6V Supply Dual-interface Architecture RapidS Serial Interface: 66MHz Maximum Clock Frequency SPI Compatible Modes 0 and 3 Rapid8 8-bit Interface: 50MHz Maximum Clock Frequency User Configurable Page Size 1024-Bytes per Page 1056-Bytes per Page 64-megabit Page Size Can Be Factory Pre-configured for 1024-Bytes Page Program Operation 2.7V Dual-interface Intelligent Programming Operation 8192 Pages (1024-/1056-Bytes/Page) Main Memory DataFlash Flexible Erase Options Page Erase (1-Kbyte) Block Erase (8-Kbytes) AT45DB642D Sector Erase (256-Kbytes) Chip Erase (64Mbits) (Not Recommended Two SRAM Data Buffers (1024-/1056-Bytes) Allows Receiving of Data while Reprogramming the Flash Array for New Designs) Continuous Read Capability through Entire Array Ideal for Code Shadowing Applications Low-power Dissipation 10mA Active Read Current Typical Serial Interface 10mA Active Read Current Typical 8-bit Interface 25A Standby Current Typical 15A Deep Power Down Typical Hardware and Software Data Protection Features Individual Sector Permanent Sector Lockdown for Secure Code and Data Storage Individual Sector Security: 128-byte Security Register 64-byte User Programmable Space Unique 64-byte Device Identifier JEDEC Standard Manufacturer and Device ID Read 100,000 Program/Erase Cycles Per Page Minimum Data Retention 20 Years Green (Pb/Halide-free/RoHS Compliant) Packaging Options Temperature Range Industrial: -40C to +85C 3542NDFLASH2/20141. Description AT45DB642D is a 2.7V, dual-interface sequential access Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. AT45DB642D supports RapidS serial interface and Rapid8 8-bit interface. RapidS serial interface is SPI compatible for frequencies up to 66MHz. The dual-interface allows a dedicated serial interface to be connected to a DSP and a dedicated 8-bit interface to be connected to a microcontroller or vice versa. However, the use of either interface is purely optional. Its 69,206,016-bits of memory are organized as 8,192 pages of 1,024-bytes (binary page size) or 1,056-bytes (standard Data- Flash page size) each. In addition to the main memory, the AT45DB642D also contains two SRAM buffers of 1,024-(binary buffer size) bytes/1,056-bytes (standard DataFlash buffer size) each. The buffers allow receiving of data while a page in the main Memory is being repro- grammed, as well as writing a continuous data stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-contained three step read-modify-write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a par- allel interface, the DataFlash uses either a RapidS serial interface or a 8-bit Rapid8 interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial appli- cations where high-density, low-pin count, low-voltage and low-power are essential. To allow for simple in-system reprogrammability, the AT45DB642D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB642D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK), or an 8-bit interface consisting of the input/output pins (I/O7 - I/O0) and the clock pin (CLK). All programming and erase cycles are self-timed. 2 AT45DB642D 3542NDFLASH2/2014