AT45DQ161 16-Mbit DataFlash, 2.3V Minimum SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support Features Single 2.3V - 3.6V supply Serial Peripheral Interface (SPI) compatible Supports SPI modes 0 and 3 Supports RapidS operation Supports Dual-input and Quad-input Buffer Write Supports Dual-output and Quad-output Read Very high operating frequencies 85MHz (for SPI) 85MHz (for Dual-I/O and Quad-I/O) Clock-to-output time (t ) of 6ns maximum V User configurable page size 512 bytes per page 528 bytes per page (default) Page size can be factory pre-configured for 512 bytes Two fully independent SRAM data buffers (512/528 bytes) Allows receiving data while reprogramming the main memory array Flexible programming options Byte/Page Program (1 to 512/528 bytes) directly into main memory Buffer Write Buffer to Main Memory Page Program Flexible erase options Page Erase (512/528 bytes), Block Erase (4KB) Sector Erase (128KB), Chip Erase (16-Mbits) Program and Erase Suspend/Resume Advanced hardware and software data protection features Individual sector protection Individual sector lockdown to make any sector permanently read-only 128-byte, One-Time Programmable (OTP) Security Register 64 bytes factory programmed with a unique identifier 64 bytes user programmable Hardware and software controlled reset options JEDEC Standard Manufacturer and Device ID Read Low-power dissipation 500nA Ultra-Deep Power-Down current (typical) 3A Deep Power-Down current (typical) 25A Standby current (typical) 11mA Active Read current (typical at 20MHz) Endurance: 100,000 program/erase cycles per page minimum (50,000 cycles for extended temperature option) Data retention: 20 years Complies with full industrial temperature range (extended temperature optional) Green (Pb/Halide-free/RoHS compliant) packaging options 8-lead SOIC (0.150 wide and 0.208 wide) 8-pad Ultra-thin DFN (5 x 6 x 0.6mm) 9-ball Ultra-thin UBGA (6 x 6 x 0.6mm) 8790EDFLASH1/2017Description The AT45DQ161 is a 2.3V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of digital voice, image, program code, and data storage applications. The AT45DQ161 also supports Dual-I/O, Quad-I/O and the RapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of memory are organized as 4,096 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DQ161 also contains two SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed. Interleaving between both buffers can dramatically increase a system s ability to write a continuous data 2 stream. In addition, the SRAM buffers can be used as additional system scratch pad memory, and E PROM emulation (bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high- density, low-pin count, low-voltage, and low-power are essential. To allow for simple in-system re-programmability, the AT45DQ161 does not require high input voltages for programming. The device operates from a single 2.3V to 3.6V power supply for the erase and program and read operations. The AT45DQ161 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). All programming and erase cycles are self-timed. 1. Pin Configurations and Pinouts Figure 1-1. Pinouts 8-lead SOIC 8-pad UDFN 9-ball UBGA Top View Top View Top View (I/O1) SI (I/O0) 1 8 SO SI (I/O ) 1 8 SO (I/O ) 0 1 2 7 GND SCK SCK GND V CC SCK 2 7 GND V RESET (I/O3) 3 6 CC RESET (I/O ) 3 6 V CC 3 CS 4 5 CS NC WP (I/O2) WP 4 5 CS WP (I/O ) 2 SO SI RST Note: 1. The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential. This pad can be a no connect or connected to GND. AT45DQ161 2 8790EDFLASH1/2017