DA14580 FINAL Bluetooth Low Energy 4.2 SoC 42 kB System SRAM General Description 84 kB ROM The DA14580 integrated circuit has a fully integrated 8 kB Retention SRAM radio transceiver and baseband processor for Blue- Power management tooth low energy. It can be used as a standalone Integrated Buck/Boost DC-DC converter application processor or as a data pump in hosted sys- P0, P1, P2 and P3 ports with 3.3 V tolerance tems. Easy decoupling of only 4 supply pins The DA14580 supports a flexible memory architecture Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V) for storing Bluetooth profiles and custom application battery cells code, which can be updated over the air (OTA). The 10-bit ADC for battery voltage measurement qualified Bluetooth low energy protocol stack is stored Digital controlled oscillators in a dedicated ROM. All software runs on the ARM 16 MHz crystal (20 ppm max) and RC oscillator Cortex -M0 processor via a simple scheduler. 32 kHz crystal (50 ppm, 500 ppm max) and RCX oscillator The Bluetooth low energy firmware includes the General purpose, Capture and Sleep timers L2CAP service layer protocols, Security Manager Digital interfaces (SM), Attribute Protocol (ATT), the Generic Attribute General purpose I/Os: 14 (WLCSP34 package), Profile (GATT) and the Generic Access Profile (GAP). 24 (QFN40 package), 32 (QFN48 package) All profiles published by the Bluetooth SIG as well as 2 UARTs with hardware flow control up to 1 MBd custom profiles are supported. SPI+ interface The transceiver interfaces directly to the antenna and I2C bus at 100 kHz, 400 kHz is fully compliant with the Bluetooth 4.2 standard. 3-axes capable Quadrature Decoder Analog interfaces The DA14580 has dedicated hardware for the Link 4-channel 10-bit ADC Layer implementation of Bluetooth low energy and Radio transceiver interface controllers for enhanced connectivity capabili- Fully integrated 2.4 GHz CMOS transceiver ties. Single wire antenna: no RF matching or RX/TX switching required Features Supply current at VBAT3V: Complies with Bluetooth V4.2, ETSI EN 300 328 and TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC) EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 0 dBm transmit output power (US) and ARIB STD-T66 (Japan) -20 dBm output power in Near Field Mode Processing power -93 dBm receiver sensitivity 16 MHz 32 bit ARM Cortex-M0 with SWD inter- Packages: face WLCSP 34 pins, 2.436 mm x 2.436 mm Dedicated Link Layer Processor QFN 40 pins, 5 mm x 5 mm AES-128 bit encryption Processor QFN 48 pins, 6 mm x 6 mm Memories KGD (wafer, dice) 32 kB One-Time-Programmable (OTP) memory System Diagram Datasheet Revision 3.4 09-Nov-2016 CFR0011-120-01 1 of 155 2014 Dialog SemiconductorDA14580 FINAL Bluetooth Low Energy 4.2 SoC Contents General Description . 1 Features . 1 System Diagram 1 Contents . 2 1 Block Diagram 3 2 Pinout . 4 3 Ordering Information 8 4 System Overview 9 4.1 ARM CORTEX M0 CPU 9 4.2 BLUETOOTH SMART 9 4.2.1 BLE Core . 9 4.2.2 Radio Transceiver . 10 4.2.3 SmartSnippets 4.3 MEMORIES 11 4.4 FUNCTIONAL MODES .11 4.5 POWER MODES . 12 4.6 INTERFACES . 12 4.6.1 UARTs 12 4.6.2 SPI+ 12 4.6.3 I2C Interface . 12 4.6.4 General Purpose ADC 13 4.6.5 Quadrature Decoder . 13 4.6.6 Keyboard Controller 13 4.6.7 Input/Output Ports . 13 4.7 TIMERS 13 4.7.1 General Purpose Timers 13 4.7.2 Wake-Up timer 14 4.7.3 Watchdog Timer . 14 4.8 CLOCK/RESET 14 4.8.1 Clocks 14 4.8.2 Reset . 15 4.9 POWER MANAGEMENT 15 5 Registers . 18 6 Specifications 139 7 Package Information . 151 7.1 MOISTURE SENSITIVITY LEVEL (MSL) . 151 7.2 WLCSP HANDLING . 151 7.3 SOLDERING INFORMATION 151 7.4 PACKAGE OUTLINES . 152 Datasheet Revision 3.4 09-Nov-2016 CFR0011-120-00-FM 2 of 155 2014 Dialog Semiconductor