DA14581 FINAL Bluetooth Low Energy 4.2 SoC with Optimized Boot Time AES-128 bit encryption Processor General Description Memories The DA14581 integrated circuit is an optimized version 32 kB One-Time-Programmable (OTP) memory of the DA14580, offering a reduced boot time and sup- 42 kB System SRAM porting up to 8 connections. It has a fully integrated 84 kB ROM radio transceiver and baseband processor for Blue- 8 kB Retention SRAM tooth low energy. It can be used as a standalone Power management application processor or as a data pump in hosted sys- Integrated Buck/Boost DC-DC converter tems. P0, P1 and P2 ports with 3.3 V tolerance The DA14581 supports a flexible memory architecture Easy decoupling of only 4 supply pins for storing Bluetooth profiles and custom application Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V) code, which can be updated over the air (OTA). The battery cells qualified Bluetooth low energy protocol stack and the 10-bit ADC for battery voltage measurement HCI ready software are stored in a dedicated ROM. All Digital controlled oscillators software runs on the ARM Cortex -M0 processor via 16 MHz crystal (20 ppm max) and RC oscillator a simple scheduler. 32 kHz crystal (50 ppm, 500 ppm max) and RCX oscillator The Bluetooth low energy firmware includes the General purpose, Capture and Sleep timers L2CAP service layer protocols, Security Manager Digital interfaces (SM), Attribute Protocol (ATT), the Generic Attribute Gen. purpose I/Os: 14 (WLCSP34), 24 (QFN40) Profile (GATT) and the Generic Access Profile (GAP). 2 UARTs with hardware flow control up to 1 MBd All profiles published by the Bluetooth SIG as well as SPI+ interface custom profiles are supported. I2C bus at 100 kHz, 400 kHz The transceiver interfaces directly to the antenna and 3-axes capable Quadrature Decoder is fully compliant with the Bluetooth 4.2 standard. Analog interfaces 4-channel 10-bit ADC The DA14581 has dedicated hardware for the Link Radio transceiver Layer implementation of Bluetooth low energy and Fully integrated 2.4 GHz CMOS transceiver interface controllers for enhanced connectivity capabili- Single wire antenna: no RF matching or RX/TX ties. switching required Supply current at VBAT3V: Features TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC) Complies with Bluetooth V4.2, ETSI EN 300 328 and 0 dBm transmit output power EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 -20 dBm output power in Near Field Mode (US) and ARIB STD-T66 (Japan) -93 dBm receiver sensitivity Supports up to 8 Bluetooth low energy connections Packages: Fast cold boot in less than 30 ms Ultra-Thin WLCSP 34 pins, 2.436 mm x 2.436 mm Processing power x 0.334 mm 16 MHz 32 bit ARM Cortex-M0 with SWD inter- WLCSP 34 pins, 2.436 mm x 2.436 mm face x 0.511 mm Dedicated Link Layer Processor QFN 40 pins, 5 mm x 5 mm System Diagram Datasheet Revision 3.2 17-Jan-2017 CFR0011-120-01 1 of 233 2014 Dialog SemiconductorDA14581 FINAL Bluetooth Low Energy 4.2 SoC with Optimized Boot Time Contents General Description . 1 11.4 GENERAL CLOCK CONSTRAINTS . 31 Features . 1 12 OTP Controller 32 12.1 OPERATING MODES 32 System Diagram 1 12.2 AHB MASTER INTERFACE . 32 Contents . 2 13 I2C Interface 33 1 Block Diagram 4 13.1 I2C BUS TERMS 33 2 Pinout . 5 13.1.1 Bus Transfer Terms . 34 13.2 I2C BEHAVIOR . 34 3 Ordering Information 8 13.2.1 START and STOP Generation . 35 4 System Overview 9 13.2.2 Combined Formats . 35 4.1 INTERNAL BLOCKS . 9 13.3 I2C PROTOCOLS . 35 4.2 FUNCTIONAL MODES . 9 13.3.1 START and STOP Conditions . 35 4.3 OTP MEMORY LAYOUT 10 13.3.2 Addressing Slave Protocol 35 4.3.1 OTP Header 10 13.3.3 Transmitting and Receiving Protocols . 36 4.4 SYSTEM START PROCEDURE 11 13.4 MULTIPLE MASTER ARBITRATION 38 4.4.1 Power/Wake-Up Sequence 12 13.5 CLOCK SYNCHRONIZATION . 39 4.4.2 OTP Mirroring 13 13.6 OPERATION MODES 40 4.4.3 BootROM Sequence . 14 13.6.1 Slave Mode Operation . 40 4.5 POWER SUPPLY CONFIGURATION 16 13.6.2 Master Mode Operation 42 4.5.1 Power Domains . 16 13.6.3 Disabling the I2C Controller . 42 4.5.2 Power Modes . 17 14 UART . 43 4.5.3 Retention Registers 17 14.1 UART (RS232) SERIAL PROTOCOL 44 5 Reset . 19 14.2 IRDA 1.0 SIR PROTOCOL 44 5.1 POR, HW AND SW RESET 19 14.3 CLOCK SUPPORT 45 14.4 INTERRUPTS 46 6 ARM Cortex-M0 20 14.5 PROGRAMMABLE THRE INTERRUPT 46 6.1 INTERRUPTS . 21 14.6 SHADOW REGISTERS 48 6.2 SYSTEM TIMER (SYSTICK) 22 14.7 DIRECT TEST MODE 48 6.3 WAKE-UP INTERRUPT CONTROLLER . 22 15 SPI+ Interface 49 6.4 REFERENCE . 22 15.1 OPERATION WITHOUT FIFOS 49 7 AMBA Bus Overview 23 15.2 9 BITS MODE 50 8 Patch Block . 24 16 Quadrature Decoder . 53 9 Memory Map 25 17 Wake-Up Timer . 54 10 Memory Controller 27 18 General Purpose Timers 55 10.1 ARBITRATION . 27 18.1 TIMER 0 55 11 Clock Generation 28 18.2 TIMER 2 57 11.1 CRYSTAL OSCILLATORS 28 19 Watchdog Timer 59 11.1.1 FRequency Control (16 MHz Crystal) . 28 20 Keyboard Controller . 60 11.1.2 Automated Trimming Mechanism 28 11.2 RC OSCILLATORS 29 20.1 KEYBOARD SCANNER 60 11.2.1 Frequency Calibration . 29 20.2 GPIO INTERRUPT GENERATOR 60 11.3 SYSTEM CLOCK GENERATION . 30 Datasheet Revision 3.2 17-Jan-2017 CFR0011-120-01 2 of 233 2014 Dialog Semiconductor