DA14583-01F01AT2 Dialog Semiconductor

DA14583 FINAL Bluetooth Low Energy 4.2 SoC with Flash Memory AES-128 bit encryption Processor General Description Memories The DA14583 integrated circuit has a fully integrated 1 Mbit Flash memory radio transceiver and baseband processor for Blue- 32 kB One-Time-Programmable (OTP) memory tooth low energy. It can be used as a standalone 42 kB System SRAM application processor or as a data pump in hosted sys- 84 kB ROM tems. 8 kB Retention SRAM The DA14583 supports a flexible memory architecture, Power management including 1 Mbit of Flash memory, for storing Bluetooth Integrated Buck mode DC-DC converter profiles and custom application code, which can be Embedded charge pump for Flash programming updated over the air (OTA). The qualified Bluetooth low P0, P1, and P2 ports with 3.3 V tolerance energy protocol stack is stored in a dedicated ROM. All Supports coin (typ. 3.0 V) battery cells software runs on the ARM Cortex -M0 processor via 10-bit ADC for battery voltage measurement a simple scheduler. Digital controlled oscillators 16 MHz crystal (20 ppm max) and RC oscillator The Bluetooth low energy firmware includes the 32 kHz crystal (50 ppm, 500 ppm max) and L2CAP service layer protocols, Security Manager RCX oscillator (SM), Attribute Protocol (ATT), the Generic Attribute General purpose, Capture and Sleep timers Profile (GATT) and the Generic Access Profile (GAP). Digital interfaces All profiles published by the Bluetooth SIG as well as 24 general purpose I/Os custom profiles are supported. 2 UARTs with hardware flow control up to 1 MBd The transceiver interfaces directly to the antenna and SPI+ interface is fully compliant with the Bluetooth 4.2 standard. I2C bus at 100 kHz, 400 kHz 3-axes capable Quadrature Decoder The DA14583 has dedicated hardware for the Link Analog interfaces Layer implementation of Bluetooth low energy and 4-channel 10-bit ADC interface controllers for enhanced connectivity capabili- Radio transceiver ties. Fully integrated 2.4 GHz CMOS transceiver Single wire antenna: no RF matching or RX/TX Features switching required Complies with Bluetooth V4.2, ETSI EN 300 328 and Supply current at VBAT3V: EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC) (US) and ARIB STD-T66 (Japan) 0 dBm transmit output power Processing power -20 dBm output power in Near Field Mode 16 MHz 32 bit ARM Cortex-M0 with SWD inter- -93 dBm receiver sensitivity face Packages: Dedicated Link Layer Processor QFN 40 pins, 5 mm x 5 mm System Diagram Datasheet Revision 3.0 04-Nov-2016 CFR0011-120-01 1 of 230 2014 Dialog SemiconductorDA14583 FINAL Bluetooth Low Energy 4.2 SoC with Flash Memory Contents 1 Block Diagram 4 13 I2C Interface 34 13.1 I2C BUS TERMS 34 2 Pinout . 5 13.1.1 Bus Transfer Terms . 35 3 Ordering Information 8 13.2 I2C BEHAVIOR . 35 13.2.1 START and STOP Generation . 36 4 System Overview 9 13.2.2 Combined Formats . 36 4.1 INTERNAL BLOCKS . 9 13.3 I2C PROTOCOLS . 36 4.2 FUNCTIONAL MODES 10 13.3.1 START and STOP Conditions . 36 4.3 OTP MEMORY LAYOUT 10 13.3.2 Addressing Slave Protocol 36 4.3.1 OTP Header .11 13.3.3 Transmitting and Receiving Protocols . 37 4.4 SYSTEM START PROCEDURE . 12 13.4 MULTIPLE MASTER ARBITRATION 39 4.4.1 Power/Wake-up Sequence 12 13.5 CLOCK SYNCHRONIZATION . 40 4.4.2 OTP Mirroring 13 13.6 OPERATION MODES 41 4.4.3 BootROM Sequence . 14 13.6.1 Slave Mode Operation . 41 4.5 POWER SUPPLY CONFIGURATION 17 13.6.2 Master Mode Operation 43 4.5.1 Power Domains . 17 13.6.3 Disabling the I2C Controller . 43 4.5.2 Power Modes . 18 4.5.3 Retention Registers 18 14 UART . 44 14.1 UART (RS232) SERIAL PROTOCOL 45 5 Reset . 20 14.2 IRDA 1.0 SIR PROTOCOL 45 5.1 POR, HW AND SW RESET 20 14.3 CLOCK SUPPORT 46 6 ARM Cortex-M0 21 14.4 INTERRUPTS 47 6.1 INTERRUPTS . 22 14.5 PROGRAMMABLE THRE INTERRUPT 47 6.2 SYSTEM TIMER (SYSTICK) 23 14.6 SHADOW REGISTERS 49 6.3 WAKE-UP INTERRUPT CONTROLLER . 23 14.7 DIRECT TEST MODE 49 6.4 REFERENCE . 23 15 SPI+ Interface 50 7 AMBA Bus Overview 24 15.1 OPERATION WITHOUT FIFOS 50 15.2 9 BITS MODE 51 8 Patch Block . 25 16 Quadrature Decoder . 54 9 Memory Map 26 17 Wake-Up Timer . 55 10 Memory Controller 28 10.1 ARBITRATION . 28 18 General Purpose Timers 56 18.1 TIMER 0 56 11 Clock Generation 29 18.2 TIMER 2 58 11.1 CRYSTAL OSCILLATORS 29 11.1.1 Frequency Control (16 MHz Crystal) 29 19 Watchdog Timer 60 11.1.2 Automated Trimming Mechanism 29 20 Keyboard Controller . 61 11.2 RC OSCILLATORS 30 20.1 KEYBOARD SCANNER 61 11.2.1 Frequency Calibration . 30 20.2 GPIO INTERRUPT GENERATOR 61 11.3 SYSTEM CLOCK GENERATION . 31 11.4 GENERAL CLOCK CONSTRAINTS . 32 21 Input/Output Ports . 63 21.1 PROGRAMMABLE PIN ASSIGNMENT 63 12 OTP Controller 33 21.2 GENERAL PURPOSE PORT REGISTERS . 63 12.1 OPERATING MODES 33 21.2.1 Port Data Register 64 12.2 AHB MASTER INTERFACE . 33 21.2.2 Port Set Data Output Register . 64 Datasheet Revision 3.0 04-Nov-2016 CFR0011-120-01 2 of 230 2014 Dialog Semiconductor