DA14680 FINAL Bluetooth Low Energy 4.2 SoC with FLASH Supports Li-Polymer, Li-Ion, coin, NiMH and alka- General description line batteries The DA14680 is a flexible System-on-Chip combining Charger (up to 5.0 V) with programmable curves an application processor, memories, cryptography High accuracy state-of-charge fuel gauge engine, power management unit, digital and analog Programmable threshold for brownout detection peripherals and a Bluetooth Smart MAC engine and Digitally controlled oscillators and PLL radio transceiver. 16/32 MHz crystal oscillator The DA14680 is based on an ARM Cortex -M0 CPU 16 MHz RC oscillator delivering up to 84 DMIPS and provides a flexible 32 kHz crystal and RC oscillator memory architecture, enabling code execution from 11.7 kHz RCX oscillator embedded memory (RAM, ROM) or non-volatile mem- Low power PLL up to 96 MHz ory (FLASH, OTP). Three general purpose timer/counters with PWM One 16-bit up/down timer/counter with PWM The advanced power management unit of the available in Extended sleep mode DA14680 enables it to run from primary and secondary Application cryptographic engine with ECC, AES- batteries, as well as provide power to external devices. 256, SHA-1, SHA-256, SHA-512 and True Random The on-chip charger and state-of-charge fuel gauge Number Generator allow the DA14680 to natively charge rechargeable Digital interfaces batteries over USB. 31 general purpose I/Os with programmable volt- An on-chip PLL enables on-the-fly tuning of the system age levels clock between 32 kHz and 96 MHz to meet high pro- Two UARTs, one with hardware flow control cessing requirements. Several optimised sleep modes Two SPI+ interfaces are available to reduce power dissipation when there is Two I2C-bus interfaces at 100 kHz, 400 kHz no activity. Three-axes capable Quadrature Decoder PDM + HW decimator (2 mics or 2 speakers) Features I2S/PCM master/slave interface up to 8 channels Keyboard scanner with debouncing Complies to Bluetooth v4.2, ETSI EN 300 328 and Infrared (IR) interface (PWM) EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 USB 1.1 Full Speed (FS) device interface (US) and ARIB STD-T66 (Japan) Analog interfaces Flexible processing power 8-channel 10-bit ADC with averaging capability 0 Hz up to 96 MHz 32-bit ARM Cortex-M0 with Three matched white LED drivers 4-way associative cache Temperature sensor Three optimised power modes (Extended sleep, Radio transceiver Deep sleep and Hibernation) reducing current to 2.4 GHz CMOS transceiver with integrated balun 1.4 uA 50 matched single wire antenna interface Memories 0 dBm transmit output power 8 Mbit FLASH memory -94 dBm receiver sensitivity (BLE) 64 kB One-Time-Programmable (OTP) memory Supply current at VBAT1 (3 V): 128 kB Data SRAM with retention capabilities TX: 3.4 mA 16 kB Cache SRAM with retention capabilities RX: 3.1 mA (with ideal DC-DC converter) 128 kB ROM (including boot ROM and BLE stack) Packages: Power management aQFN with 60 pins, 6 mm x 6 mm Integrated Buck DC-DC converter (1.7 V to 4.5 V) Three power supply pins for external devices System diagram Datasheet Revision 3.0 28-February-2018 CFR0011-120-00-FM Rev 5 1 of 454 2018 Dialog SemiconductorDA14680 FINAL Bluetooth Low Energy 4.2 SoC with FLASH 1.0 Block diagram . 6 8.0 AMBA Bus . 42 2.0 Package and pinout 7 9.0 Memory Controller 43 3.0 System overview . 16 10.0 OTP Controller 45 3.1 INTERNAL BLOCKS 16 10.1 OPERATING MODES 45 3.2 FUNCTIONAL MODES 17 10.2 AHB MASTER INTERFACE . 46 3.3 SYSTEM CONFIGURATION . 17 10.3 AHB SLAVE INTERFACES 46 3.4 SYSTEM STARTUP PROCEDURE 20 10.4 ERROR CORRECTING CODE (ECC) . 46 3.4.1 Power/Wakeup FSM . 21 10.5 BUILD-IN SELF REPAIR (BISR) 46 3.4.2 Goto Sleep FSM 21 11.0 Quad SPI Controller 47 3.4.3 BootROM sequence . 22 11.1 ARCHITECTURE 48 3.5 POWER CONTROL AND MODES . 25 11.1.1 Interface 48 3.5.1 System Power Control 25 11.1.2 Initialization FSM . 48 3.5.2 Power domains . 25 11.1.3 SPI modes 49 3.5.3 Power modes . 27 11.1.4 Access modes . 49 4.0 Reset . 29 11.1.5 Endianess 49 4.1 POR, HW AND SW RESET 29 11.1.6 Erase Suspend/Resume . 49 4.2 BROWN OUT DETECTION 30 11.2 PROGRAMMING 51 11.2.1 Auto Mode 51 5.0 Clock generation . 31 11.2.2 Manual Mode 51 5.1 CLOCK TREE . 31 11.2.3 Clock selection . 51 5.2 CRYSTAL OSCILLATORS . 32 11.2.4 Received data . 52 5.2.1 Frequency control (16 MHz crystal) 32 12.0 DMA Controller 53 5.2.2 Automated trimming and settling notification 32 12.1 DMA PERIPHERALS 54 5.2.3 Using a 32 MHz crystal . 33 12.2 INPUT/OUTPUT MULTIPLEXER . 54 5.3 RC OSCILLATORS . 34 12.3 DMA CHANNEL OPERATION . 54 5.3.1 Frequency calibration 34 12.4 DMA ARBITRATION . 55 5.4 PLL . 34 12.5 FREEZING DMA CHANNELS 55 6.0 ARM Cortex M0 . 35 13.0 AES/Hash Engine 56 6.1 SYSTEM TIMER (SYSTICK) 36 13.1 DESCRIPTION . 56 6.2 WAKEUP INTERRUPT CONTROLLER . 36 13.2 ARCHITECTURE . 57 6.3 REFERENCE . 36 13.2.1 AES/HASH engine 57 6.4 INTERRUPTS . 37 13.2.2 AES . 57 13.2.3 Modes . 58 7.0 Cache Controller . 39 13.2.4 HASH 58 7.1 CACHABLE RANGE 39 13.3 PROGRAMMING . 59 7.2 RUNTIME RECONFIGURATION 40 14.0 ECC Engine . 61 7.2.1 Cache Line reconfiguration 40 7.2.2 TAG memory word . 40 14.1 ARCHITECTURE . 61 7.2.3 Associativity reconfiguration . 40 14.1.1 Supported curves . 62 7.3 2 AND 4 WAY REPLACEMENT STRATEGY . 40 14.1.2 Supported high level algorithms 62 7.4 CACHE RESETS . 40 15.0 True Random Number Generator (TRNG) 63 7.5 CACHE MISS RATE MONITOR . 41 15.1 ARCHITECTURE . 63 15.2 PROGRAMMING . 63 15.2.1 Latency 63 Datasheet Revision 3.0 28-February-2018 CFR0011-120-00-FM Rev 5 2 of 454 2018 Dialog Semiconductor