DA14681 FINAL Bluetooth Low Energy 4.2 SoC line batteries General description Charger (up to 5.0 V) with programmable curves The DA14681 is a flexible System-on-Chip combining High accuracy state-of-charge fuel gauge an application processor, memories, cryptography Programmable threshold for brownout detection engine, power management unit, digital and analog Digitally controlled oscillators and PLL peripherals and a Bluetooth Low Energy MAC engine 16 MHz crystal oscillator and radio transceiver. 16 MHz RC oscillator The DA14681 is based on an ARM Cortex -M0 CPU 32 kHz crystal and RC oscillator delivering up to 84 DMIPS and provides a flexible 11.7 kHz RCX oscillator memory architecture, enabling code execution from Low power PLL up to 96 MHz embedded memory (RAM, ROM) or non-volatile mem- Three general purpose timer/counters with PWM ory (OTP or external Quad-SPI FLASH). One 16-bit up/down timer/counter with PWM available in extended/deep sleep mode The advanced power management unit of the Application cryptographic engine with ECC, AES- DA14681 enables it to run from primary and secondary 256, SHA-1, SHA-256, SHA-512 and True Random batteries, as well as provide power to external devices. Number Generator The on-chip charger and state-of-charge fuel gauge Digital interfaces allow the DA14681 to natively charge rechargeable 37 (AQFN) or 21 (WLCSP) general purpose I/Os batteries over USB. with programmable voltage levels An on-chip PLL enables on-the-fly tuning of the system Quad-SPI FLASH interface clock between 32 kHz and 96 MHz to meet high pro- Two UARTs, one with hardware flow control cessing requirements. Several optimised sleep modes Two SPI+ interfaces are available to reduce power dissipation when there is Two I2C bus interfaces at 100 kHz, 400 kHz no activity. Three-axes capable Quadrature Decoder PDM + HW decimator (2 mics or 2 speakers) Features I2S/PCM master/slave interface up to 8 channels Keyboard scanner with debouncing Complies to Bluetooth v4.2, ETSI EN 300 328 and Infrared (IR) interface (PWM) EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 USB 1.1 Full Speed (FS) device interface (US) and ARIB STD-T66 (Japan) Analog interfaces Flexible processing power 8-channel 10-bit ADC with averaging capability 0 Hz up to 96 MHz 32-bit ARM Cortex-M0 with Three matched white LED drivers 4-way associative cache Temperature sensor Three optimised power modes (Extended sleep, Radio transceiver Deep sleep and Hibernation) reducing current to 2.4 GHz CMOS transceiver with integrated balun 1.4 uA 50 matched single wire antenna interface Memories 0 dBm transmit output power 64 kB One-Time-Programmable (OTP) memory -94 dBm receiver sensitivity (BLE) 128 kB Data SRAM with retention capabilities Supply current at VBAT1 (3 V): 16 kB Cache SRAM with retention capabilities TX: 3.4 mA 128 kB ROM (including boot ROM and BLE stack) RX: 3.1 mA (with ideal DC-DC converter) Power management Packages: Integrated Buck DC-DC converter (1.7 V - 4.75 V) AQFN with 60 pins, 6 mm x 6 mm Three power supply pins for external devices WLCSP with 53 balls, 3.406 mm x 3.010 mm Supports Li-Polymer, Li-Ion, coin, NiMH and alka- System diagram Datasheet Revision 3.0 28-February-2018 CFR0011-120-00-FM Rev 5 1 of 459 2018 Dialog SemiconductorDA14681 FINAL Bluetooth Low Energy 4.2 SoC 1 Block diagram 6 8.2 RUNTIME RECONFIGURATION 58 8.2.1 Cache Line reconfiguration 58 2 Package and pinout . 7 8.2.2 TAG memory word . 58 3 System overview . 19 8.2.3 Associativity reconfiguration . 58 3.1 INTERNAL BLOCKS 19 8.3 2 AND 4 WAY REPLACEMENT STRATEGY . 58 3.2 FUNCTIONAL MODES 20 8.4 CACHE RESETS . 58 3.3 SYSTEM CONFIGURATION . 20 8.5 CACHE MISS RATE MONITOR . 59 3.4 SYSTEM STARTUP PROCEDURE 23 8.6 CACHE MISS LATENCY AND POWER . 59 3.4.1 Power/Wakeup FSM . 24 9 AMBA Bus 61 3.4.2 Goto Sleep FSM 24 10 Memory Controller 63 3.4.3 BootROM sequence . 25 3.5 POWER CONTROL AND MODES . 27 11 OTP Controller 65 3.5.1 System Power Control 27 11.1 OPERATING MODES 65 3.5.2 Power domains . 28 11.2 AHB MASTER INTERFACE . 66 3.5.3 Power modes . 29 11.3 AHB SLAVE INTERFACES 66 4 Power management 31 11.4 ERROR CORRECTING CODE (ECC) . 66 11.5 BUILD-IN SELF REPAIR (BISR) 66 4.1 ARCHITECTURE 31 4.1.1 SIMO DC-DC converter . 32 12 Quad SPI Controller . 67 4.1.2 LDOs . 34 12.1 ARCHITECTURE . 67 4.1.3 Switching from DC-DC to LDOs 36 12.1.1 Interface 67 4.1.4 PMU configurations in Sleep modes . 37 12.1.2 Initialization FSM . 68 4.1.5 Wake/Power up - Sleep Timing . 37 12.1.3 SPI modes 69 4.1.6 Charger . 40 12.1.4 Access modes . 69 4.1.7 Fuel gauge . 42 12.1.5 Endianess 69 4.1.8 USB charger detection 44 12.1.6 Erase Suspend/Resume . 69 5 Reset . 47 12.1.7 QSPI FLASH Programming . 70 12.2 PROGRAMMING . 70 5.1 POR, HW AND SW RESET 47 12.2.1 Auto Mode 70 5.2 BROWN OUT DETECTION 48 12.2.2 Manual Mode 71 6 Clock generation . 49 12.2.3 Clock selection . 71 6.1 CLOCK TREE . 49 12.2.4 Received data . 71 6.2 CRYSTAL OSCILLATORS . 50 12.3 TIMING . 71 6.2.1 Frequency control (16 MHz crystal) 50 13 DMA Controller . 73 6.2.2 Automated trimming and settling notification 13.1 DMA PERIPHERALS 74 50 13.2 INPUT/OUTPUT MULTIPLEXER . 74 6.3 RC OSCILLATORS . 51 13.3 DMA CHANNEL OPERATION . 74 6.3.1 Frequency calibration 52 13.4 DMA ARBITRATION . 75 6.4 PLL . 52 13.5 FREEZING DMA CHANNELS 75 7 ARM Cortex M0 53 14 AES/Hash Engine . 76 7.1 SYSTEM TIMER (SYSTICK) 54 14.1 DESCRIPTION . 76 7.2 WAKEUP INTERRUPT CONTROLLER . 54 14.2 ARCHITECTURE . 77 7.3 REFERENCE . 54 14.2.1 AES/HASH engine 77 7.4 INTERRUPTS . 55 14.2.2 AES . 77 8 Cache Controller . 57 14.2.3 Modes . 78 8.1 CACHABLE RANGE 57 14.2.4 HASH 78 Datasheet Revision 3.0 28-February-2018 CFR0011-120-00-FM Rev 5 2 of 459 2018 Dialog Semiconductor