SLG46121 GreenPAK Dual Supply Programmable Mixed-signal Matrix Features Pin Configuration Logic & Mixed Signal Circuits Highly Versatile Macrocells 1.8 V (5%) to 5 V (10%) VDD 1.8 V (5%) to 5 V (10%) VDD2 (VDD2 VDD) Operating Temperature Range: -40C to 85C 10 1 12 11 RoHS Compliant / Halogen-Free VDD GPIO Pb-Free 12-pin STQFN: 1.6 x 1.6 x 0.55 mm, 0.4 mm pitch 9 2 GPIO GPI 8 3 GPIO GPIO Applications 7 4 5 6 GND GPIO Personal Computers and Servers PC Peripherals Consumer Electronics Data Communications Equipment Handheld and Portable Electronics STQFN-12 (Top View) Block Diagram Pin 12 Pin 11 GPIO VDD2 Look Up Tables (LUTs) Combination Function Macrocells ACMP0 2-bit 2-bit 2-bit 2-bit LUT2 4 LUT2 0 LUT2 1 LUT2 2 or DFF0 or DFF1 or DFF2 Pin 1 Pin 10 3-bit 3-bit VDD GPIO LUT3 4 LUT3 5 3-bit 2bit 3-bit LUT3 1 LUT2 3 LUT3 0 3-bit 3-bit or DFF5 or DFF3 or DFF4 LUT2 6 LUT3 7 ACMP1 3-bit 3-bit 3-bit Pin 2 Pin 9 LUT3 8 or LUT3 2 LUT3 3 GPI GPIO Pipe Delay or DFF6 or DFF7 Additional Combination Functions 4bit 4-bit Additional LUT4 0 LUT4 1 Logic FILTER 0/Prog. Delay or CNT2 or CNT3 Functions Pin 3 Pin 8 GPIO GPIO INV 0 RC Oscillator Bandgap Counters/Delay Generators Pin 4 Pin 7 GPIO GND CNT0 CNT1 POR Vref Pin 5 Pin 6 GPIO GPIO Silego Technology, Inc. Rev 1.06 000-0046121--106 Revised October 11, 2017 GPIO GPIO GPIO VDD2SLG46121 1.0 Overview The SLG46121 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46121. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The additional power supply (VDD2) on the SLG46121 provides the ability to interface two independent voltage domains within the same design. Users can configure pins, dedicated to each power supply, as inputs, outputs, or both (controlled dynamically by internal logic) to both VDD and VDD2 voltage domains. Using the available macrocells designers can implement mixed-signal functions bridging both domains or simply pass through level-translation in both High to Low and Low to High directions. The macrocells in the device include the following: Two Analog Comparators (ACMP) Voltage References (Vref) Five Combinatorial Look Up Tables (LUTs) One 2-bit LUTs Four 3-bit LUTs Twelve Combination Function Macrocell Four Selectable DFF/Latch or 2-bit LUTs Four Selectable DFF/Latch or 3-bit LUTs One Selectable Pipe Delay or 3-bit LUT Pipe Delay 8 stage / 2 output, one 1 stage fixed output Two Selectable Counter/Delay or 4-bit LUT One Programmable Delay / Deglitch Filter Two Counter / Delay Generators (CNT/DLY) One 8-bit counter/delay One 14-bit counter/delay with external clock/reset Eight D Flip-Flop / Latches (DFF) (Part of Combination Function Macrocell) Additional Logic Function - 1 Inverter Pipe Delay 8 stage/2 output (Part of Combination Function Macrocell) One Bandgap RC Oscillator (RC OSC) Power On Reset (POR) 000-0046121--106 Page 1 of 97