SLG46721V-SKT Dialog Semiconductor

SLG46721 GreenPAK Programmable Mixed Signal Array Features Pin Configuration Logic & Mixed Signal Circuits Highly Versatile Macrocells Read Back Protection (Read Lock) 1.8 V (5%) to 5 V (10%) Supply Operating Temperature Range: -40C to 85C VDD 1 17 GPIO RoHS Compliant / Halogen-Free 2 16 GPI 20 19 18 GPIO 20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch 3 15 GPIO GPIO Applications 4 14 GPIO GPIO Personal Computers and Servers GPIO 5 13 GPIO PC Peripherals 8 9 10 GPIO 6 12 GPIO Consumer Electronics Data Communications Equipment 7 11 GPIO GND Handheld and Portable Electronics STQFN-20 (Top View) Block Diagram Pin 20 Pin 19 Pin 18 GPIO GPIO GPIO Pin 17 Pin 1 GPIO VDD Counters/Delay Generators Look Up Tables (LUTs) Pin 16 Pin 2 GPIO GPI 2-bit 2-bit 3-bit ACMP0 CNT0 CNT1 CNT4 LUT2 4 LUT2 5 LUT3 0 CNT5 CNT6 3-bit 3-bit 3-bit LUT3 1 LUT3 4 LUT3 5 Pin 15 Pin 3 GPIO GPIO 3-bit 3-bit 3-bit LUT3 6 LUT3 7 LUT3 9 ACMP1 Additional Logic Functions Pin 14 INV 0 INV 1 Pin 4 GPIO GPIO Combination Function Macrocells FILTER 1 FILTER 0 2-bit 2-bit 2-bit ACMP2 LUT2 0 LUT2 1 LUT2 2 or DFF4 or DFF5 or DFF6 Pin 13 Pin 5 GPIO GPIO 2-bit 3bit 3-bit LUT2 3 LUT3 2 LUT3 3 RC Oscillator Vref or DFF7 or DFF2 or DFF3 ACMP3 3-bit 4-bit 4-bit Pin 12 Pin 6 LUT3 8 or LUT4 0 LUT4 1 GPIO GPIO Pipe Delay or CNT2 or CNT3 Programmable POR Delay Pin 11 Pin 7 GND GPIO Pin 8 Pin 9 Pin 10 GPIO GPIO GPIO Revision 1.18 2019 Dialog Semiconductor Revised October 29, 2019 GPIO GPIO GPIO GPIO GPIO GPIOSLG46721 1.0 Overview The SLG46721 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46721. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macrocells in the device include the following: Four Analog Comparators (ACMP) Two Voltage References (Vref) Nine Combinatorial Look Up Tables (LUTs) Two 2-bit LUTs Seven 3-bit LUTs Nine Combination Function Macrocells Four Selectable DFF/Latch or 2-bit LUTs Two Selectable DFF/Latch or 3-bit LUTs One Selectable Pipe Delay or 3-bit LUT Two Selectable CNT/DLY or 4-bit LUTs Five Counter / Delay Generators (CNT/DLY) One 14-bit delay/counter One 14-bit delay/counter with external clock/reset Three 8-bit delays/counters Pipe Delay 16 stage/3 output (Part of Combination Function Macrocell) Programmable Delay Additional Logic Functions Two Inverters Two Deglitch Filters RC Oscillator (RC OSC) Revision 1.18 2019 Dialog Semiconductor Page 1 of 100