SLG46824G Dialog Semiconductor

SLG46824 GreenPAK Programmable Mixed Signal Matrix with In System PRELIMINARY Programmability Programmable Delay with Edge Detector Output General Description Deglitch Filter with Edge Detector The SLG46824 provides a small, low power component for Three Oscillators (OSC) commonly used mixed-signal functions. The user creates the 2.048 kHz Oscillator circuit design by programming the multiple time Non-Volatile 2.048 MHz Oscillator Memory (NVM) to configure the interconnect logic, the IOs 25 MHz Oscillator and the macrocells of the SLG46824. This highly versatile Power On Reset (POR) device allows a wide variety of mixed-signal functions to be In System Programmability designed within a very small, low power single integrated cir- Multiple Time Programmable Memory cuit. Wide Range Power Supply 2.5 V (8%) to 5 V (10%) V DD Key Features 1.8 V (5%) to 5 V (10%) V (V V ) DD2 DD2 DD Two Low Power General Purpose Rail-to-Rail Analog Operating Temperature Range: -40C to 85C Comparators (ACMPxL) RoHS Compliant / Halogen-Free One Voltage Reference (Vref) Two Packages Available One Vref Output 20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch Eleven Combination Function Macrocells 20-pin TSSOP: 6.5 x 6.4 x 1.2 mm, 0.65 mm pitch Three Selectable DFF/Latch or 2-bit LUTs One Selectable Programmable Pattern Generator or 2- bit LUT Six Selectable DFF/Latch or 3-bit LUTs One Selectable Pipe Delay or Ripple Counter or 3-bit LUT Eight Multi-Function Macrocells Seven Selectable DFF/Latch or 3-bit LUTs + 8-bit Delay/ Counters One Selectable DFF/Latch or 4-bit LUT + 16-bit Delay/ Counter Serial Communications 2 I C Protocol Interface Applications Personal Computers and Servers PC Peripherals Consumer Electronics Data Communications Equipment Handheld and Portable Electronics Smartphones and Fitness Bands Notebook and Tablet PCs Datasheet Revision <2.0> 29-Dec-2017 1 of 148 CFR0011-120-01 2017 Dialog SemiconductorSLG46824 GreenPAK Programmable Mixed Signal Matrix with In System PRELIMINARY Programmability Contents 1 Block Diagram ......................................................................................................................................................................7 2 Pinout ....................................................................................................................................................................................8 2.1 Pin Configuration - STQFN- 20L ............................................................................................................................8 2.2 Pin Configuration - TSSOP-20L .............................................................................................................................9 3 Characteristics ...................................................................................................................................................................13 3.1 Absolute Maximum Ratings .................................................................................................................................13 3.2 Recommended Operating Conditions .................................................................................................................13 3.3 Electrical Characteristics ......................................................................................................................................13 3.4 Timing Characteristics .........................................................................................................................................17 3.5 OSC Characteristics .............................................................................................................................................19 3.6 ACMP Specifications ............................................................................................................................................21 4 Functional Description ......................................................................................................................................................23 4.1 IO Pins .................................................................................................................................................................23 4.2 GPIO Pins ............................................................................................................................................................23 4.3 GPO Pins .............................................................................................................................................................23 4.4 GPI Pins ...............................................................................................................................................................23 4.5 Pull Up/Down Resistors .......................................................................................................................................23 4.6 Fast Pull-up/down during Power up .....................................................................................................................23 4.7 I2C Mode IO Structure (VDD or VDD2) ...............................................................................................................23 4.8 Matrix OE IO Structure (VDD or VDD2) ...............................................................................................................24 4.9 Register OE IO Structure (VDD or VDD2) ...........................................................................................................25 4.10 Register OE IO Structure (for IOs 0, 2, 3 with VDD) .........................................................................................25 4.11 Register OE IO Structure (VDD or VDD2) .........................................................................................................26 5 Connection Matrix ..............................................................................................................................................................27 5.1 Matrix Input Table ................................................................................................................................................28 5.2 Matrix Output Table .............................................................................................................................................29 5.3 Connection Matrix Virtual Inputs ..........................................................................................................................32 5.4 Connection Matrix Virtual Outputs .......................................................................................................................33 6 Combination Function Macrocells ....................................................................................................................................34 6.1 2-Bit LUT or D Flip Flop Macrocells .....................................................................................................................34 6.4 3-Bit LUT or Pipe Delay / Ripple Counter Macrocell ............................................................................................47 7 Multi-Function Macrocells .................................................................................................................................................52 7.1 3-Bit LUT or 8- Bit Counter / Delay Macrocells ....................................................................................................52 7.2 CNT/DLY/FSM Timing Diagrams .........................................................................................................................61 7.3 4-Bit LUT or 16-Bit Counter / Delay Macrocell .....................................................................................................69 8 Analog Comparators ..........................................................................................................................................................71 8.1 ACMP0L Block Diagram ....................................................................................................................................72 8.2 ACMP1L Block Diagram .....................................................................................................................................73 9 Programmable Delay / Edge Detector ..............................................................................................................................74 9.1 Programmable Delay Timing Diagram - Edge Detector Output ...........................................................................74 10 Additional Logic Function. Deglitch Filter .....................................................................................................................75 11 Voltage Reference (VREF) ...............................................................................................................................................76 11.1 Voltage Reference Overview .............................................................................................................................76 11.2 VREF Selection Table .......................................................................................................................................76 11.3 VREF Block Diagram ........................................................................................................................................77 12 Clocking ............................................................................................................................................................................78 12.1 Oscillator0 (2.048 kHz) .......................................................................................................................................79 12.2 Oscillator1 (2.048 MHz) .....................................................................................................................................80 12.3 Oscillator2 (25 MHz) ..........................................................................................................................................81 12.4 Clock Scheme ...................................................................................................................................................82 12.5 External Clocking ...............................................................................................................................................82 13 Power On Reset (POR) .....................................................................................................................................................83 13.1 General Operation ..............................................................................................................................................83 13.2 POR Sequence ..................................................................................................................................................84 13.3 Macrocells Output States During POR Sequence .............................................................................................84 14 I2C Serial Communications Macrocell ...........................................................................................................................87 Datasheet Revision <2.0> 29-Dec-2017 2 of 148 CFR0011-120-01 2017 Dialog Semiconductor