SLG46826VTR Dialog Semiconductor

SLG46826 GreenPAK Programmable Mixed Signal Matrix with In-System PRELIMINARY Programmability Serial Communications General Description 2 I C Protocol Interface The SLG46826 provides a small, low power component for 2 2-Kbit (256 x 8) I C-Compatible (2-Wire) Serial EEPROM commonly used mixed-signal functions. The user creates the emulation with Software Write Protection circuit design by programming the multiple time Non-Volatile Programmable Delay with Edge Detector Output Memory (NVM) to configure the interconnect logic, the IOs Deglitch Filter with Edge Detector and the macrocells of the SLG46826. This highly versatile Three Oscillators (OSC) device allows a wide variety of mixed-signal functions to be 2.048 kHz Oscillator designed within a very small, low power single integrated cir- 2.048 MHz Oscillator cuit. 25 MHz Oscillator Analog Temperature Sensor Key Features Power On Reset (POR) Two High Speed General Purpose Rail-to-Rail Analog In System Programmability Comparators (ACMPxH) Multiple Time Programmable Memory Two Low Power General Purpose Rail-to-Rail Analog Wide Range Power Supply Comparators (ACMPxL) 2.5 V (8%) to 5 V (10%) V DD Two Voltage References (Vref) 1.8 V (5%) to 5 V (10%) V (V V ) DD2 DD2 DD Two Vref Outputs Operating Temperature Range: -40C to 85C Eleven Combination Function Macrocells RoHS Compliant / Halogen-Free Three Selectable DFF/Latch or 2-bit LUTs Two Packages Available One Selectable Programmable Pattern Generator or 20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch 2-bit LUT 20-pin TSSOP: 6.5 x 6.4 x 1.2 mm, 0.65 mm pitch Six Selectable DFF/Latch or 3-bit LUTs One Selectable Pipe Delay or Ripple Counter or 3-bit LUT Eight Multi-Function Macrocells Seven Selectable DFF/Latch or 3-bit LUTs + 8-bit Delay/Counters One Selectable DFF/Latch or 4-bit LUT + 16-bit Delay/Counter Applications Personal Computers and Servers PC Peripherals Consumer Electronics Data Communications Equipment Handheld and Portable Electronics Smartphones and Fitness Bands Notebook and Tablet PCs Datasheet Revision <2.1> 12-Jan-2018 1 of 155 2018 Dialog Semiconductor CFR0011-120-01SLG46826 GreenPAK Programmable Mixed Signal Matrix with In-System PRELIMINARY Programmability Contents 1 Block Diagram ......................................................................................................................................................................7 2 Pinout ....................................................................................................................................................................................8 2.1 Pin Configuration - STQFN- 20L ............................................................................................................................8 2.2 Pin Configuration - TSSOP-20L .............................................................................................................................9 3 Characteristics ...................................................................................................................................................................13 3.1 Absolute Maximum Ratings .................................................................................................................................13 3.2 Recommended Operating Conditions .................................................................................................................13 3.3 Electrical Characteristics ......................................................................................................................................13 3.4 Timing Characteristics .........................................................................................................................................17 3.5 OSC Characteristics .............................................................................................................................................19 3.6 ACMP Specifications ............................................................................................................................................21 3.7 Analog Temperature sensor (ts) specifications ....................................................................................................23 4 IO Pins .................................................................................................................................................................................25 4.1 IO Pins .................................................................................................................................................................25 4.2 GPIO Pins ............................................................................................................................................................25 4.3 GPO Pins .............................................................................................................................................................25 4.4 GPI Pins ...............................................................................................................................................................25 4.5 Pull Up/Down Resistors .......................................................................................................................................25 4.6 Fast Pull-up/down during Power up .....................................................................................................................25 4.7 I2C Mode IO Structure (VDD or VDD2) ...............................................................................................................25 4.8 Matrix OE IO Structure (VDD or VDD2) ...............................................................................................................26 4.9 Register OE IO Structure (VDD or VDD2) ...........................................................................................................27 4.10 Register OE IO Structure (for IOs 0, 2, 3 with VDD) .........................................................................................27 4.11 Register OE IO Structure (VDD or VDD2) .........................................................................................................28 5 Connection Matrix ..............................................................................................................................................................29 5.1 Matrix Input Table ................................................................................................................................................30 5.2 Matrix Output Table .............................................................................................................................................31 5.3 Connection Matrix Virtual Inputs ..........................................................................................................................34 5.4 Connection Matrix Virtual Outputs .......................................................................................................................35 6 Combination Function Macrocells ....................................................................................................................................36 6.1 2-Bit LUT or D flip-flop Macrocells .......................................................................................................................36 6.4 3-Bit LUT or Pipe Delay / Ripple Counter Macrocell ............................................................................................49 7 Multi-Function Macrocells .................................................................................................................................................54 7.1 3-Bit LUT or 8- Bit Counter / Delay Macrocells ....................................................................................................54 7.2 CNT/DLY/FSM Timing Diagrams .........................................................................................................................63 7.3 4-Bit LUT or 16-Bit Counter / Delay Macrocell .....................................................................................................71 8 ACMPxH BG/analog start up time BG/analog start up timeAnalog Comparators .......................................................................................................................77 8.1 ACMP0H Block Diagram .....................................................................................................................................77 8.2 ACMP1H Block Diagram ......................................................................................................................................77 8.3 ACMP2L Block Diagram ......................................................................................................................................77 8.4 ACMP3L Block Diagram .....................................................................................................................................77 9 Programmable Delay / Edge Detector ..............................................................................................................................78 9.1 Programmable Delay Timing Diagram - Edge Detector Output ...........................................................................78 10 Additional Logic Function. Deglitch Filter .....................................................................................................................79 11 Voltage Reference (VREF) ...............................................................................................................................................80 11.1 Voltage Reference Overview .............................................................................................................................80 11.2 VREF Selection Table .......................................................................................................................................80 11.3 VREF Block Diagram ........................................................................................................................................81 12 Clocking ............................................................................................................................................................................82 12.1 Oscillator0 (2.048 kHz) .......................................................................................................................................83 12.2 Oscillator1 (2.048 MHz) .....................................................................................................................................84 12.3 Oscillator2 (25 MHz) ..........................................................................................................................................85 12.4 Clock Scheme ...................................................................................................................................................86 Datasheet Revision <2.1> 12-Jan-2018 2 of 155 2018 Dialog Semiconductor CFR0011-120-01