74HC164 400 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS Description Pin Assignments The 74HC164 is a serial input 8-bit edge-triggered shift register that has outputs from each of eight stages. ( Top View ) SERIAL DATA INPUT PINS 14 1 Vcc DSA The serial input data is entered at pin SDA or pin SDB as these are 2 13 logically ANDED. Either input could be used as an active HIGH DSB Q7 enable with data entry on the other pin. If a single input is desired, the 3 12 Q6 Q0 pins can be tied together or the unused input can be tied HIGH. 11 4 Q5 Q1 10 5 DATA ENTRY Q2 Q4 Data is shifted into Q0 from the serial input pins on each LOW to 6 9 MR Q3 HIGH transition of the CP pin. Also during the CP edge the data is 7 8 GND CP transferred from each Qn to Qn+1. The serial data on pins DSA and DSB must be stable before and after the CP rising edge to meet the SO-14 / TSSOP-14 / PDIP-14 set-up and hold timing requirements. RESET When asserted LOW the Master Reset ( MR ) pin sets all Qn to LOW. This action does not depend on the condition of serial input or clock pins. The MR must be asserted HIGH for a recovery time before the next CP positive edge pulse. Features Applications Wide Supply Voltage Range from 2.0V to 6.0V General Purpose Logic Sinks or Sources 4mA at V = 4.5V Wide Array of Products Such as: CC CMOS Low Power Consumption PCs, Networking, Notebooks, Netbooks Schmitt Trigger Action at all Inputs Computer Peripherals, Hard Drives, CD/DVD ROM ESD Protection Exceeds JESD 22 TV, DVD, DVR, Set-Top Box 200-V Machine Model (A115) 2000-V Human Body Model (A114) Exceeds 1000-V Charged Device Model (C101) Range of Package Options SO-14 and TSSOP-14 Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. Green Device (Note 3) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See 74HC164 400 Pin Descriptions Pin Number Pin Name Function 1 DSA Serial Data Input 2 DSB Serial Data Input 3 Q0 Data Output Q1 4 Data Output 5 Q2 Data Output 6 Q3 Data Output 7 GND Ground 8 CP Clock Pulse Positive Edge Triggered 9 MR Master Reset - Asynchronous 10 Q4 Data Output 11 Q5 Data Output 12 Q6 Data Output 13 Q7 Data Output 14 V Supply Voltage CC Function Table (Note 4) Input Output Mode CP DSA DSB Q0 Q1-Q7 MR Reset L X X X L L H L X L QnQn-1 (n= 1 to7) Shift H X L L QnQn-1 (n= 1 to7) H H H H QnQn-1 (n= 1 to7) Note: 4. Signals asserted on DSA and DSB must be in place longer than Tsu (set-up time) before CP occurs and remain in place Thold (hold time) after CP. Logic Diagram 1 DSA D Q D Q D Q D Q D Q D Q D Q D Q 2 C C C C C C C C DSB R R R R R R R R 8 CP 9 MR 3 4 5 6 10 11 12 13 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 of 10 74HC164 March 2015 Diodes Incorporated www.diodes.com Document number: DS36279 Rev. 2- 2 NEW PRNOEDWU CPTR ODUCT