PI2EQX3201BL TM 3.0Gbps 2 Differential Channel SATA i/m ReDriver with Equalization, De-emphasis and OOB Features Description SATA2 i/m, extended SATA2 Pericom Semiconductors PI2EQX3201BL is a low power, signal ReDriver. The device provides programmable Two Pairs of 3.0Gbps differential signal equalization, amplification, and de-emphasis by using 4 select Adjustable Transmitter Emphasis & Amplitude bits, SEL 0:3 , to optimize performance over a variety of Adjustable Receiver Equalization physical mediums by reducing Inter-Symbol Interference. PI2EQX3201BL supports two 100-Ohm Differential CML data 100-Ohm Differential CML I/Os I/Os between the Protocol ASIC to a switch fabric, across a Input signal level detect and squelch for each channel backplane, or to extend the signals across other distant data Low Power (100mW per Channel) pathways on the users platform. Stand-by Mode Power Down State The integrated equalization circuitry provides flexibility with signal integrity of the signal before the re-driver. Whereas the V Operating Range: 1.5V to 1.8V DD integrated de-emphasis circuitry provides flexibility with signal Packaging (Pb-free & Green): integrity of the signal after the re-driver. 36-pad TQFN (ZF36) A low-level input signal detection and output squelch function is provided for each channel. Each channel operates fully independantly. When a channel is enabled (EN x=1) and operating, that channels input signal level (on xI+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to providing signal re-conditioning, Pericoms PI2EQX3201BL also provides power management Stand-by mode operated by a Bus Enable pin. Pin Description (Top-Side View) Block Diagram Signal Detection 33 36 35 34 32 31 30 29 V 1 28 DD V DD + A AI CML 2 27 0+ - A CML AI 3 26 0- xO+ xl+ GND 4 25 GND Limiting Equalizer Amp V 5 24 GND DD GND xO- xl- V 6 23 V DD DD 0:1 X SEL + B 7 22 BI 0+ SEL2 x SEL3 x - B 8 21 BI 0- 9 20 GND GND Power V 10 19 DD NC EN X Management 11 12 13 14 15 16 17 18 Repeated 2 Times - 10-0220 PS9003A 09/07/10 1 NC SD A NC SD B SEL0 B SEL0 A SEL1 B SEL1 A SEL2 B SEL2 A SEL3 B SEL3 A NC EN A NC EN BPI2EQX3201BL 3.0Gbps 2 Differential Channel Serial ReDriver Equalization, De-emphasis and Squelch Pin Description Pin Pin Name I/O Description 2 AI+ I CML Input Channel A with internal 50-Ohm pull down 3 AI- 27 AO+ CML Output Channel A internal 50-Ohm pull up. Drives to output common mode O 26 AO- voltage when input is <V . TH 22 BI+ I CML Input Channel B with internal 50-Ohm pull down 21 BI- 7 BO+ CML Output Channel B with internal 50-Ohm pull up. Drives to output common O 8 BO- mode voltage when input is <V . TH 30 EN A EN A:B is the enable pin. A LVCMOS high provides normal operation. A LVC- I 29 EN B MOS low selects a low power down mode. 4, 9, 20, 24, 25, GND PWR Supply Ground Center Pad 11, 12, 17, 18, 19 NC - No Connect Signal Detect, output for channels A and B. Provides a LVCMOS high output when 36 SD A O a valid input signal is detected. When low, SD X indicates that the input signal 35 SD B level is below the signal detect threshold level. 34 SEL0 A I 33 SEL1 A Selection pins for equalizer (see Amplifier Configuration Table) w/ 25K-Ohm internal pull up 13 SEL0 B I 14 SEL1 B 32 SEL2 A I Selection pins for amplifier (see Amplifier Configuration Table) w/ 25K-Ohm internal pull up 15 SEL2 B I 31 SEL3 A I Selection pins for De-Emphasis (See De-Emphasis Configuration Table) w/ 25K-Ohm internal pull up 16 SEL3 B I 1, 5, 6, 10, 23, 28 V PWR 1.5 to 1.8V Supply Voltage (0.1V) DD Output De-emphasis Adjustment Output Swing Control SEL3 A:B De-emphasis SEL2 A:B Swing 0 0dB 0 1x 1 -3.5dB 1 1.2x Equalizer Selection SEL0 A:B SEL1 A:B Compliance Channel 1.5GHz 0 0 no equalization 0 1 1.5dB 1.0dB 1 0 3.5dB 1.0dB 1 1 5.5dB 1.0dB PS9003A 09/07/10 10-0220 2