PI2EQX3202B 3.2Gbps, 4 Differential Channel, Serial ReDriver with Equalization, De-emphasis, and Squelch Features Description Supports data rates up to 3.2Gbps on each lane Pericom Semiconductors PI2EQX3202B is a low power, signal ReDriver. The device provides programmable equalization, Optimized for SATA i/m operation ampli cation, and de-emphasis by using 7 select bits, SEL 0:6 , Adjustable Transmiter De-Emphasis & Amplitude to optimize performance over a variety of physical mediums by Adjustable Receiver Equalization reducing Inter-symbol Interference. PI2EQX3202B supports four 100-Ohm Differential CML data I/Os between the Protocol ASIC Two Spread Spectrum Reference Clock Buffer Outputs to a switch fabric, across a backplane, or to extend the signals Optimized for SATA applications across other distant data pathways on the users platform. Input signal level detection & output squelch on all channels The integrated equalization circuitry provides exibility with 100-Ohm Differential CML I/Os signal integrity of the signal before the ReDriver. Whereas the integrated de-emphasis circuitry provides exibility with signal Low Power (100mW per Channel) integrity of the signal after the ReDriver. Standby Mode Power Down State A low-level input signal detection and output squelch function V Operating Range: 1.5V to 1.8V DD is provided for all four channels. Each channel operates fully Industrial temperture range independently. When a channel is enabled (EN x=1) and operating, that channels input signal level (on xI+/-) determines Packaging (Pb-free & Green): 84-ball LFBGA (NB84) whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to providing signal re-conditioning, Pericoms PI2EQX3202B also provides power management Stand-by mode operated by an Enable pin. Block Diagram Pin Description 1 2 3 4 5 6 7 8 9 10 LVCMOS A SD C SD D SEL0 A SEL0 B SEL4 A SEL4 B SEL6 A SEL6 B EN A EN B Signal Detection SD x B V SD B V SEL1 A SEL2 A SEL3 A SEL5 A V EN C V DD DD DD DD CML C BO+ SD A AI+ SEL1 B SEL2 B SEL3 B SEL5 B BI+ EN D AO+ CML xO+ xI+ Limiting D BO V AI BI GND AO Equalizer DD Amp xO- xI- E GND V GND GND GND GND DD SE L 0:2 84-Ball LFBGA F V GND V V GND V Power DD DD DD DD SE L 2 x SE L 3 x EN x Management G DO+ SEL0 C CI+ DI+ SEL6 C CO+ -- Repeated 2 times -- H DO SEL0 D CI V CKIN+ CKIN GND DI SEL6 D CO DD CKIN- OUT- Bu f fe r CKIN+ EN OUT+ J GND SEL1 C GND SEL2 C SEL2 D SEL3 D IREF GND SEL4 D GND CLK IREF OUT0+ OUT0 OUT1+ OUT1 K EN CLK SEL1 D SEL3 C SEL4 C SEL5 C SEL5 D 09-0019 PS8885G 07/31/09 1PI2EQX3202B 3.2Gbps, 4 Differential Channel, Serial ReDriver with Equalization, De-emphasis, and Squelch Pin Description Pin Pin Name I/O Description B1, F1, D2, E2, B3, F3, H4, B8, V PWR Supply Voltage, 1.5V to 1.8V 0.1V DD F8, B10, F10 C3 AI+ I CML Input Channel A with internal 50 pull down D3 AI- E1, J1, F2, E3, J3, H7, E8, J8, GND PWR Supply Ground D9, E9, F9, E10, J10 C8 BI+ I CML Input Channel B with internal 50 pull down D8 BI- G3 CI+ I CML Input Channel C with internal 50 pull down H3 CI- G8 DI+ I CML Input Channel D with internal 50 pull down H8 DI- A3, B4, B5 SEL 0:2 A I A4, C4, C5 SEL 0:2 B I Selection pins for equalizer (see Ampli er Con guration Table) w/ 50k internal pull up G2, J2, J4 SEL 0:2 C I H2, K2, J5 SEL 0:2 D I B6, A5 SEL 3:4 A I C6, A6 SEL 3:4 B I Selection pins for ampli er (see Ampli er Con guration Table) w/ 50k internal pull up K3, K4 SEL 3:4 C I J6, J9 SEL 3:4 D I B7, A7 SEL 5:6 A I C7, A8 SEL 5:6 B I Selection pins for De-Emphasis (See De-Emphasis Con guration Table) w/ 50k internal pull up K9, G9 SEL 5:6 C I K10, H9 SEL 5:6 D I C10 AO+ CML Output Channel A internal 50 pull up to V during normal operation and DD O D10 AO- 2k when EN A=0. Drives to output common mode voltage when input is <V . TH CML Output Channel B with internal 50 pull up to V during normal opera- DD C1 BO+ O tion and 2k when EN B=0. Drives to output common mode voltage when input is D1 BO- <V . TH CML Output Channel C with internal 50 pull up to V during normal opera- DD G10 CO+ O tion and 2k when EN C=0. Drives to output common mode voltage when input is H10 CO- <V . TH CMLOutput Channel D with internal 50 pull up to V during normal operation DD G1 DO+ O and 2k when EN D=0. Drives to output common mode voltage when input is H1 DO- <V . TH Active HIGH LVCMOS signal input pins, when HIGH, it enables the CML output. EN A9, A10, B9, C9 I When LOW, it disables the CML output (x0+, x0-) to HI-z state. Both x0+ & x0- out- A,B,C,D puts will be pulled up to V by internal 2k resistor. DD (Continued) PS8885G 07/31/09 09-0019 2