PI2EQX3211B 3.2Gbps 2 Differential Channel Serial Re-driver with Equalization, Squelch and Flow-Through Pinout Features Description SATA s/m output drive Pericom Semiconductors PI2EQX3211B is a low power, signal re-driver. The device provides programmable equalization, by Two 3.2Gbps differential channels using 2 select bits, EQA and EQB, to optimize performance Adjustable Receiver Equalization over a variety of physical mediums by reducing Inter-Symbol 100-Ohm Differential CML I/Os Interference. PI2EQX3211B supports two 100-Ohm Differential CML data I/Os between the Protocol ASIC to a switch fabric, Input signal level detect and squelch for each channel across a backplane, or to extend the signals across other distant Low Power (100mW per Channel) data pathways on the users platform. Stand-by Mode Power Down State The integrated equalization circuitry provides exibility with V Operating Range: 1.5V to 1.8V CC signal integrity of the signal before the re-driver. Whereas the integrated de-emphasis circuitry provides exibility with signal Packaging (Pb-free & Green): integrity of the signal after the re-driver. 20-lead SSOP A low-level input signal detection and output squelch function is provided for each channel. Each channel operates fully independantly. When the channels are enabled (EN=1) and operating, that channels input signal level (on xI+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to providing signal re-conditioning, Pericoms PI2EQX3211B also provides power management Stand-by mode operated by the Enable pin. Pin Description Block Diagram Signal Detection EQA 1 20 EN VDD 2 19 VDD CML AI+ AO+ 3 18 CML xO+ AI- xl+ AO- 4 17 GND GND 5 16 Limiting Equalizer Amp VDD VDD 6 15 xl- xO- BO+ BI+ 7 14 BO- BI- EQx 8 13 GND GND 9 12 -Repeated 2 times- EQB VDD 10 11 Power EN Management PS8901B 05/16/08 08-0113 1PI2EQX3211B 3.2Gbps 2 Differential Channel Serial Re-driver Equalization, Squelch and Flow-Through Pinout Pin Description Pin Pin Name I/O Description 3 AI+ I Positive CML Input Channel A with internal 50 pull down 4 AI- I Negative CML Input Channel A with internal 50 pull down Positive CML Output Channel A with internal 50 pull up to VDD during normal 18 AO+ O operation and 2k when EN=0. Drives to output common mode voltage when input is <V . TH Negative CML Output Channel A with internal 50 pull up to VDD during normal 17 AO- O operation and 2k when EN=0. Drives to output common mode voltage when input is <V . TH 14 BI+ I Positive CML Input Channel B with internal 50 pull down 13 BI- I Negative CML Input Channel B with internal 50 pull down Positive CML Output Channel B with internal 50 pull up to VDD during normal 7 BO+ O operation and 2k when EN=0. Drives to output common mode voltage when input is <V . TH Negative CMLOutput Channel B with internal 50 pull up to VDD during normal 8 BO- O operation and 2k when EN=0. Drives to output common mode voltage when input is <V . TH EN is the enable pin. A LVCMOS high provides normal operation. A LVCMOS 20 EN I low selects a low power down mode. 5, 9, 12, 16 GND PWR Supply Ground 1 EQA I Selection pins for equalizer (see Equalizer Selection Table) w/ 50K internal pull up 10 EQB I 2, 6, 11, 15, 19 V PWR Supply Voltage, 1.5V to 1.8V (0.1V) DD Equalizer Selection EQx Compliance Channel 0 0:2.5dB 1.6 GHz 1 4.5:6.5dB 1.6 GHz PS8901B 05/16/08 08-0113 2