PI2EQX4402D 2.5 Gbps x2 Lane Serial PCI Express Repeater/Equalizer with Signal Detect feature Description Features Pericom Semiconductors PI2EQX4402D is a low power, Two High Speed PCI Express lanes PCI Express compliant signal Re-Driver. The device provides Supports PCI Express data rates (2.5 Gbps) on each lane programmable equalization, amplification, and de-emphasis Adjustable Transmiter De-Emphasis & Amplitude by using 7 select bits, SEL 0:6 , to optimize performance over a variety of physical mediums by reducing Inter-symbol Adjustable Receiver Equalization interference. PI2EQX4402D supports four 100-ohm Differential Input Signal Level Detect & Output Squelch on all Channels CML data I/Os between the Protocol ASIC to a switch fabric, Two Spread Spectrum Reference Clock Buffer Outputs across a backplane, or extends the signals across other distant data 100 Differential CML I/Os pathways on the users platform. The integrated equalization circuitry provides flexibility with Low Power (100mW per Channel) signal integrity of the PCI Express signal before the Re-Driver. Standby Mode Power Down State Whereas the integrated de-emphasis circuitry provides flexibility V Operating Range: 1.8V +/-0.1V DD with signal integrity of the PCI Express signal after the Re- Packaging (Pb-free & Green): 84-ball LFBGA (NB84) Driver. A low-level input signal detection and output squelch function is provided for all four channels. Each channel operates fully independantly. When a channel is enabled (EN x=1) and operating, that channel input signal level (on xl+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the output driver switches off, and the pin is pulled to VDD via a high impedance resistor. In addition to providing signal re-conditioning, Pericoms PI2EQX4402D also provides power management Stand-by mode operated by an Enable pin. A differential clock buffer is provided for test and other system requirements. This clock function is not used by the data channels. Block Diagram Pin Description (Top View) 1 2 3 4 5 6 7 8 9 10 A SD C SD D SEL0 A SEL0 B SEL4 A SEL4 B SEL6 A SEL6 B EN A EN B CML CML xO+ xI+ B V SD B V SEL1 A SEL2 A SEL3 A SEL5 A V EN C V DD DD DD DD Limiting Equalizer Amp C BO+ SD A AI+ SEL1 B SEL2 B SEL3 B SEL5 B BI+ EN D AO+ xO- xI- D BO V AI BI GND AO DD 84-Ball LFBGA SEL 0:2 E GND V GND GND GND GND Power DD SEL 3:4 x SEL 5:6 x Management EN x F V GND V V GND V DD DD DD DD -- Repeated 4 times -- G DO+ SEL0 C CI+ DI+ SEL6 C CO+ CKIN- OUT0- H DO SEL0 D CI V CKIN+ CKIN GND DI SEL6 D CO Buffer DD CKIN+ OUT0+ EN CLK OUT1- J GND SEL1 C GND SEL2 C SEL2 D SEL3 D IREF GND SEL4 D GND OUT1+ IREF OUT0+ OUT0 OUT1+ OUT1 K EN CLK SEL1 D SEL3 C SEL4 C SEL5 C SEL5 D 12-0256 PS8875C 07/17/07 1PI2EQX4402D 2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer with Signal Detect feature Pin Description Pin Pin Name I/O Description B1, F1, D2, E2, B3, F3, H4, B8, V PWR 1.8V Supply Voltage DD F8, B10, F10 Positive CML Input Channel A with internal 50 pull down during normal operation C3 AI+ I (EN A=1). When EN A=0, this pin is high impedance. Negative CML Input Channel A with internal 50 pull down during normal operation D3 AI- I (EN A=1). When EN A=0, this pin is high impedance. E1, J1, F2, E3, J3, H7, E8, J8, D9, GND PWR Supply Ground E9, F9, E10, J10 Positive CML Input Channel B with internal 50 pull down during normal operation C8 BI+ I (EN B=1). When EN B=0, this pin is high impedance. Negative CML Input Channel B with internal 50 pull down during normal operation D8 BI- I (EN B=1). When EN B=0, this pin is high impedance. Positive CML Input Channel C with internal 50 pull down during normal operation G3 CI+ I (EN C=1). When EN C=0, this pin is high impedance. Negative CML Input Channel C with internal 50 pull down during normal operation H3 CI- I (EN C=1). When EN C=0, this pin is high impedance. Positive CML Input Channel D with internal 50 pull down during normal operation G8 DI+ I (EN D=1). When EN D=0, this pin is high impedance. Negative CML Input Channel D with internal 50 pull down during normal operation H8 DI- I (EN D=1). When EN D=0, this pin is high impedance. SEL 0: A3, B4, B5 I 2 A Selection pins for equalizer (see Amplifier Configuration Table) A4, C4, C5 SEL 0:2 B I w/ 50K internal pull up G2, J2, J4 SEL 0:2 C I H2, K2, J5 SEL 0:2 D I B6, A5 SEL 3:4 A I C6, A6 SEL 3:4 B I Selection pins for amplifier (see Amplifier Configuration Table) w/ 50K internal pull up K3, K4 SEL 3:4 C I J6, J9 SEL 3:4 D I B7, A7 SEL 5:6 A I C7, A8 SEL 5:6 B I Selection pins for De-Emphasis (See De-Emphasis Configuration Table) w/ 50K internal pull up K9, G9 SEL 5:6 C I K10, H9 SEL 5:6 D I Positive CML Output Channel A internal 50 pull up during normal operation and C10 AO+ O 2K pull up otherwise. Negative CML Output Channel A with internal 50 pull up during normal operation D10 AO- O and 2K pull up otherwise. Positive CML Output Channel B with internal 50 pull up during normal operation C1 BO+ O and 2K pull up otherwise. Negative CMLOutput Channel B with internal 50 pull up during normal operation D1 BO- O and 2K pull up otherwise. Positive CMLOutput Channel C with internal 50 pull up during normal operation G10 CO+ O and 2K pull up otherwise. Negative CMLOutput Channel C with internal 50 pull up during normal operation H10 CO- O and 2K pull up otherwise. PS8875C 07/17/07 12-0256 2