A product Line of Diodes Incorporated PI2EQX6804-A 6.5Gbps 4-Lane SAS2/SATA/XAUI ReDriver with Equalization & De-Emphasis Features Description Up to 6.5Gbps SAS2/SATA/XAUI ReDriver Diodes PI2EQX6804-A is a low power, SAS2, SATA, XAUI signal ReDriver. The device provides programmable equaliza - Supporting 8 differential channels or 4 ports tion, amplicfi ation, and de-emphasis by either pin strapping Pin strapped and I2C configuration controls (3.3V Tolerant) 2 option or I C control to optimize performance over a variety of Adjustable receiver equalization physical mediums by reducing Inter-symbol interference. Adjustable transmitter amplitude and de-emphasis PI2EQX6804-A supports eight 100-Ohm Differential CML data I/Os between the Protocol ASIC to a switch fabric, across a back- 50-Ohm input/output termination plane, or extends the signals across other distant data pathways Mux/Demux feature on the users platform. Channel loop-back e iTh ntegrated equalization circuitry provides flexibility with OOB fully supported signal integrity of the signal before the ReDriver, whereas the integrated de-emphasis circuitry provides flexibility with signal Single supply voltage, 1.2V 5% integrity of the signal after the ReDriver. Power down modes In addition to providing signal re-conditioning, Diodes Industrial temperature range: -40C to 85C PI2EQX6804-A also provides power management Stand-by Packaging (Pb-free & Green): 2 mode operated by a Power Down pin, or through I C register. 100-contact LBGA Block Diagram Pin Configuration (Top-Side View) 1 2 3 4 5 6 7 8 9 10 + Output Input level detect Controls to control logic VDD B0TX- B0TX+ VDD SCL SDA VDD B0RX+ B0RX- VDD A xyRx+ + xyTx+ + xyRx- Equalizer A1RX+ GND GND A0RX- DE A VDD A0TX- GND GND A1TX+ B xyTx- xyTx+ + A A1RX- GND GND A0RX+ NC PD A0TX+ GND GND A1TX- C Equalizer xyRx+ + B xyTx- xyRx- D2 A D VDD B1TX+ B1TX- VDD NC VDD B1R X- B1RX+ VDD Input level detect Output + Controls to control logic E SEL0 A SEL1 A SEL2 A D0 A D1 A S0 A NC S1 A SIG A NC Data Lane Repeats 4 Times NC SIG B S1 B NC S0 B A1 SEL2 B LB SEL1 B SEL0 B F SELy x Mode Sy x Control Registers LB - & Logic VDD A2RX A2RX+ VDD MODE D0 B VDD A2TX+ A2TX- VDD G Dy x DE x B2TX+ GND GND B3TX - DE B A0 B3RX- GND GND B2RX+ H Power PD Management J B2TX- GND GND B3TX+ NC D1 B B3RX+ GND GND B2RX- SDA 2 I C Control Ax SCL VDD A3RX+ A3RX- VDD D2 B A4 VDD A3TX- A3TX+ K VDD PI2EQX6804-A www.diodes.com July 2017 1 Document Number: DS39966 Rev1-2 Diodes IncorporatedA product Line of Diodes Incorporated PI2EQX6804-A Pin Description Pin Pin Name Type Description Data Signals C4 A0RX+, I CML inputs for Channel A0, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). B4 A0RX- I C7 A0TX+, O CML outputs for Channel A0, with internal 50-Ohm pull-up. Goes to high-impedance during power-down (PD =0). B7 A0TX- O B1 A1RX+, I CML inputs for Channel A1, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). C1 A1RX- I B10 A1TX+, O CML outputs for Channel A1, with internal 50-Ohm pull-up. Goes to high-impedance during power-down (PD =0). C10 A1TX- O G3 A2RX+, I CML inputs for Channel A2, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). G2 A2RX- I G8 A2TX+, O CML outputs for Channel A2, with internal 50-Ohm pull-up. Goes to high-impedance during power-down (PD =0). G9 A2TX- O K2 A3RX+, I CML inputs for Channel A3 with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). K3 A3RX- I K9 A3TX+, O CML outputs for Channel A3, with internal 50-Ohm pull-up. Goes to high-impedance during power-down (PD =0). K8 A3TX- O A8 B0RX+, I CML inputs for Channel B0, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). A9 B0RX- I A3 B0TX+, O CML outputs for Channel B0, with internal 50-Ohm pull-up. Goes to high-impedance during power-down (PD =0). A2 B0TX- O D9 B1RX+, I CML inputs for Channel B1, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). D8 B1RX- I D2 B1TX+, O CML outputs for Channel B1, with internal 50-Ohm pull-up. Goes to high-impedance during power-down (PD =0). D3 B1TX- O H10 B2RX+, I CML inputs for Channel B2, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). J10 B2RX- I H1 B2TX+, O CML outputs for Channel B2, with internal 50-Ohm pull-up. Goes to high-impedance during power-down (PD =0). J1 B2TX- O J7 B3RX+, I CML inputs for Channel B3, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). H7 B3RX- I J4 B3TX+, O CML outputs for Channel B3, with internal 50-Ohm pull-up. Goes to high-impedance during power-down (PD =0). H4 B3TX- O PI2EQX6804-A www.diodes.com July 2017 2 Document Number: DS39966 Rev1-2 Diodes Incorporated