A product Line of Diodes Incorporated PI2EQX6814 6.5Gbps 4-Lane SAS2/SATA/XAUI ReDriver with Equalization & De-emphasis Features Description Up to 6.5Gbps SAS2/SATA/XAUI ReDriver Diodes PI2EQX6814 is a 6.5Gbps low power, 4 lane (8 Supporting 8 differential channels or 4 lanes channel) SAS2, SATA, XAUI signal ReDriver. Independent channel configuration e dTh evice provides programmable equalization, amplicfi ation, 2 Pin strapped and I C configuration controls (3.3V Tolerant) 2 and de-emphasis by either pin strapping or I C control, select Adjustable receiver equalization bits, to optimize performance over a variety of physical mediums Adjustable transmitter amplitude and de-emphasis by reducing Inter-symbol interference. Adjustable input threshold level PI2EQX6814 supports eight 100-Ohm Differential CML data 50-Ohm input/output termination Mux/Demux and loop-back features I/Os between the Protocol ASIC to a switch fabric, across a back- OOB fully supported plane, or extends the signals across other distant data pathways Single supply voltage, 1.2V 5% on the users platform. Active Current per channel - 95mA (typical) e iTh ntegrated equalization circuitry provides flexibility with Automatic slumber mode power savings signal integrity of the signal before the ReDriver, whereas the Slumber current per channel -10mA (typical) integrated de-emphasis circuitry provides flexibility with signal Power down Standby Mode integrity of the signal after the ReDriver. Standby current -1mA (typical) Industrial temperature range: -40C to 85C In addition to providing signal re-conditioning, Diodes PI- Packaging (Pb-free & Green): 2EQX6814 also provides power management Stand-by mode op- 100-contact LBGA (11mm x11mm) 2 erated by a Power Down pin, or through I C register. In addition, the device performs automatic Slumber Mode (Disable Transmit) during idle conditions on the receiver. Block Diagram Pin Configuration (Top-Side View) 1 2 3 4 5 6 7 8 9 10 + Output Inputlevel detect A VDD B0TX- B0TX+ VDD SCL SDA VDD B0RX+ B0RX- VDD Controls tocontrollogic + xyRx+ xyTx+ A1RX+ GND GND A0RX- DE A VDD A0TX- GND GND A1TX+ B + xyRx- Equalizer Channel A0-3 xyTx- A1RX- GND GND A0RX+ NC PD A0TX+ GND GND A1TX- C Equalizer xyTx+ + xyRx+ + VDD B1TX+ B1TX- VDD D2 A GND VDD B1RX- B1RX+ VDD D xyTx- xyRx- Inputlevel detect + Output tocontrollogic E SEL0 A SEL1 A SEL2 A GND D1 A S0 A NC S1 A SIG A NC Controls Channels B0-3 F NC SIG B S1 B NC S0 B A1 SEL2 B LB SEL1 B SEL0 B SELy x - Mode VDD A2RX A2RX+ VDD MODE GND VDD A2TX+ A2TX- VDD G Sy x Control Registers &Logic Dy x B2TX+ GND GND B3TX - DE B A0 B3RX- GND GND B2RX+ H PRE x J B2TX- GND GND B3TX+ NC D1 B B3RX+ GND GND B2RX- Power PD Management K VDD A3RX+ A3RX- VDD D2 B A4 VDD A3TX- A3TX+ VDD SDA 2 I CControl Ax SCL www.diodes.com October 2019 PI2EQX6814 1 Diodes Incorporated Document Number DS42336 Rev 1-3 A product Line of Diodes Incorporated PI2EQX6814 Pin Description Pin Pin Name Type Description Data Signals C4 A0RX+, I CML inputs for Channel A0, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). B4 A0RX- I C7 A0TX+, O CML outputs for Channel A0, with internal 50-Ohm pull-up. Goes to high- impedance during power-down (PD =0). B7 A0TX- O B1 A1RX+, I CML inputs for Channel A1, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). C1 A1RX- I B10 A1TX+, O CML outputs for Channel A1, with internal 50-Ohm pull-up. Goes to high- impedance during power-down (PD =0). C10 A1TX- O G3 A2RX+, I CML inputs for Channel A2, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). G2 A2RX- I G8 A2TX+, O CML outputs for Channel A2, with internal 50-Ohm pull-up. Goes to high- impedance during power-down (PD =0). G9 A2TX- O K2 A3RX+, I CML inputs for Channel A3 with internal 50-Ohm pull-down. Goes to high- impedance during power-down (PD =0). K3 A3RX- I K9 A3TX+, O CML outputs for Channel A3, with internal 50-Ohm pull-up. Goes to high- impedance during power-down (PD =0). K8 A3TX- O A8 B0RX+, I CML inputs for Channel B0, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). A9 B0RX- I A3 B0TX+, O CML outputs for Channel B0, with internal 50-Ohm pull-up. Goes to high- impedance during power-down (PD =0). A2 B0TX- O D9 B1RX+, I CML inputs for Channel B1, with internal 50-Ohm pull-down. Goes to high- impedance during power-down (PD =0). D8 B1RX- I D2 B1TX+, O CML outputs for Channel B1, with internal 50-Ohm pull-up. Goes to high- impedance during power-down (PD =0). D3 B1TX- O H10 B2RX+, I CML inputs for Channel B2, with internal 50-Ohm pull-down. Goes to high-impedance during power-down (PD =0). J10 B2RX- I H1 B2TX+, O CML outputs for Channel B2, with internal 50-Ohm pull-up. Goes to high- impedance during power-down (PD =0). J1 B2TX- O J7 B3RX+, I CML inputs for Channel B3, with internal 50-Ohm pull-down. Goes to high- impedance during power-down (PD =0). H7 B3RX- I J4 B3TX+, O CML outputs for Channel B3, with internal 50-Ohm pull-up. Goes to high- impedance during power-down (PD =0). H4 B3TX- O Control Signals 2 H6, F6, K6 A0, A1, A4 I I C programmable address bit A0, A1 and A4 with 100K-Ohm internal pull up E5 D1 A Selection pins for Channel Ax de-emphasis (See de-emphasis Configuration I Table) w/ 100K-Ohm internal pull up D5 D2 A www.diodes.com October 2019 PI2EQX6814 2 Diodes Incorporated Document Number DS42336 Rev 1-3