PI6C10804 1.5V/1.8V/2.5V, 180MHz, 1:4 Networking Clock Buffer Features Description High-speed, low-noise, non-inverting 1:4 buffer The PI6C10804 is a 1.5V to 2.5V high-speed, low-noise 1:4 non-inverting clock buffer. The key goal in de sign ing the Maximum Frequency up to 180 MHz PI6C10804 is to target networking applications that re quire low- Low output skew < 70ps (1.8V, 2.5V), <100ps (1.5V) skew, low-jitter, and high-frequency clock distribution. Low propagation delay < 3.0ns (1.8V, 2.5V), <3.5ns (1.5V) Providing output-to-output skew as low as 70ps, the PI6C10804 Optimized duty cycle is an ideal clock distribution de vice for syn chro nous sys tems. De- sign ing syn chro nous net work ing sys tems re quires a tight level of 1.5V - 2.5V supply voltage skew from a large number of outputs. 3.3V Tolerant input clock Packages (Pb-free & Green available): 8-pin SOIC (W) Block Diagram Pin Con guration OE CLK0 1 8 BUF IN OE CLK1 7 V 2 CLK0 DD BUF IN GND CLK1 3 6 CLK2 5 CLK3 4 CLK2 CLK3 Pin Description Pin Name Description BUF IN Input CLK 0:3 Outputs GND Ground V Power DD OE Output Enable PS8822G 10/07/09 09-0056 1PI6C10804 1.5V/1.8V/2.5V, 180MHz, 1:4 Networking Clock Buffer 2.5V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Note: Storage Temperature ...........................................................65C to +150C Stresses greater than those listed under MAXIMUM RAT INGS may cause permanent damage to the V Voltage ..........................................................................0.5V to +3.6V DD device. This is a stress rating only and functional op er a tion Output Voltage ............................................................... 0.5V to V +0.5V DD of the device at these or any other con di tions above those indicated in the operational sec tions of this spec i ca tion is Input Voltage .......................................................................................... 3.6V not implied. Ex po sure to absolute maximum rating con di - tions for extended periods may affect re li abil i ty. 2.5V DC Characteristics (Over Operating Range: V = 2.5V 0.2V, T = -40 to 85C) DD A (1) (2) Parameters Description Test Conditions Min. Typ. Max. Units V Supply Voltage 2.3 2.5 2.7 V DD V Input HIGH Voltage Logic HIGH level 1.7 3.6 IH V V Input LOW Voltage Logic LOW level -0.3 0.7 IL V = Max, V = V or DD IN DD I Input Current I pin 15 A I GND I = -1mA 2.0 OH V Output High Voltage V = Min., V = V or V I = -2mA 1.7 OH DD IN IH IL OH I = -8mA 1.5 V OH I = 1mA 0.4 OL V Output LOW Voltage V = Min., V - V or V I = 2mA 0.7 OL DD IN IH IL OL I = 8mA 0.7 V OL Notes: 1. For Max. or Min. conditions, use appropriate operating range values. 2. Typical values are at V = 2.5V, +25C ambient and maximum loading. DD 2.5V AC Characteristics (Over Operating Range: V = 2.5V 0.2V, T = -40 to 85C) DD A (1) Parameters De scrip tion Min. Typ Max. Units Test Conditions F Input Frequency 0 250 MHz IN t /t CLKn Rise/Fall Time 20% to 80% 1 ns R F (2) t t Propagation Delay BUF IN to CLKn 1.0 1.5 2.0 ns PLH, PHL Output to Output Skew between any two (3) t 70 SK(O) outputs of the same device same transition Pulse Skew between opposite transitions (3) C = 5pF, 125 MHz L t 100 200 ps SK(P) (t -t ) of the same output PHL PLH Outputs are measured Part to Part Skew between two identical out- V /2 DD (3) t 300 SK(T) (4) puts of different parts on the same board t Duty Cycle In 1ns edge rate 45 55 dc in % Duty Cycle Out 40 60 t dc out Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worse cast temperature (max. temp). 4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. PS8822G 10/07/09 2 09-0056