PI6C182 PI6C182A Precision 1-to-10 Clock Buffer Features Description Low noise non-inverting 1-to-10 buffer The PI6C182 is a high-speed low-noise 1-to-10 noninverting buf- fer designed for SDRAM clock buffer applications, supporting Supports frequency up to 125 MHz (PI6C182A) frequencies up to 110 MHz. 2 Supports up to four SDRAM DIMMs At power up all SDRAM output are enabled and active. The I C serial control may be used to individually activate/de ac ti vate any Low skew (<200ps) between any two output clocks driver. 2 I C Serial Con guration interface The output enable pin (OE) may be pulled LOW to tri-state all Multiple V and V pins for noise reduction DD SS outputs. Note: 3.3V power supply voltage 2 Purchases of I C components from Pericom conveys a license of 2 Separate Hi-Z state pin for testing use in I C system de ned by Philips Semiconductor. Packaging (Pb-free & Green available): 28-pin SSOP (H) Diagram Pin Con g u ra tion SDRAM0 V 28 1 V DD0 DD5 27 SDRAM7 SDRAM0 2 SDRAM1 SDRAM1 3 26 SDRAM6 BUF IN 25 V 4 V SS0 SS5 SDRAM2 24 V 5 V DD4 DD1 23 SDRAM2 6 SDRAM5 SDRAM3 22 SDRAM3 7 SDRAM4 21 V 8 V SS1 SS4 20 BUF IN 9 OE 19 V 10 V DD2 DD3 SDRAM9 18 SDRAM8 11 SDRAM9 OE V 12 17 V SS2 SS3 13 16 V V DDIIC SSIIC SDATA 2 I C SDATA 14 15 SCLOCK I/O SCLOCK 08-0298 PS8165G 11/13/08 1PI6C182, PI6C182A Precision 1-to-10 Clock Buffer Pin Description Pin Symbol Type Qty Description 2, 3, 6, 7 SDRAM 0-3 O 4 SDRAM Byte 0 clock output 22, 23, 26, 27 SDRAM 4-7 O 4 SDRAM Byte 1 clock output 11, 18 SDRAM 8-9 O 2 SDRAM Byte 2 clock output 9 BUF IN I 1 Input for 1-20 buffer 20 OE I 1 Hi-Z when LOW. Internal 100k pull-up resistor. 2 14 SDATA I/O 1 Data pin for I C curcuitry. Internal 100k pull-up resistor. 2 15 SCLOCK I/O 1 Clock pin I C circuitry. Internal 100k pull-up resistor. 1, 5, 10, 19, 24, VDD 0-5 Power 6 3.3V power supply for SDRAM buffers 28 4, 8, 12, 17, 21, VSS 0-5 Ground 6 Ground for SDRAM buffers 25 2 13 VDDIIC Power 1 3.3V power supply for I C circuitry 2 16 VSSIIC Ground 1 Ground for I C circuitry (1) (1,2) Serial Con guration Map OE Functionality Byte0: SDRAM Active/Inactive Register OE SDRAM 0-9 (1 = enable, 0 = disable) 0 Hi-Z Bit Pin Description 1 BUF IN 7 NC (Initialize to 0) Notes: 6 NC (Initialize to 0) 1. Used for test purposes only 2. Buffers are non-inverting 5 NC (Initialize to 0) 4 NC (Initialize to 0) 3 7 SDRAM3 (Active/Inactive) 2 I C Address Assignment 2 6 SDRAM2 (Active/Inactive) A6 A5 A4 A3 A2 A1 A0 R/W 1 3 SDRAM1 (Active/Inactive) 11010010 0 2 SDRAM0 (Active/Inactive) Note: 1. Inactive means outputs are held LOW and are disabled from switching 08-0298 PS8165G 11/13/08 2