PI6C20400A
1:4 Clock Driver for Intel PCIe Chipsets
Features Description
Phase jitter filter for PCIe 2.0 application Pericom Semiconductor's PI6C20400A is a PCIe 2.0 compliant
high-speed, low-noise differential clock buffer designed to be
Four Pairs of Differential Clocks
companion to PI6C410BS. The device distributes the differential
Low skew < 50ps
SRC clock from PI6C410BS to four differential pairs of clock
Low jitter < 50ps cycle-to-cycle
outputs either with or without PLL. The clock outputs are
controlled by input selection of SRC_STOP#, PWRDWN# and
< 1 ps additive RMS phase jitter
SMBus, SCLK and SDA. When input of either SRC_STOP#
Output Enable for all outputs
or PWRDWN# is low, the output clocks are Tristated. When
Outputs tristate control via SMBus
PWRDWN# is low, the SDA and SCLK inputs must be Tri-stated.
Programmable PLL Bandwidth
100 MHz PLL Mode operation
100 - 400 MHz Bypass Mode operation
3.3V Operation
Packaging (Pb-free and Green):
28-Pin SSOP (H28)
28-Pin TSSOP (L28)
Block Diagram Pin Configuration
OE_INV
V 28 V
DD 1 DD_A
OE_0 & OE_3
Output
SRC 27 V
2 SS_A
SRC_STOP#
Control
SRC# 26 I
PWRDWN# 3 REF
OUT0
V 25 OE_INV
SS 4
OUT0#
V 24 V
DD 5 DD
OUT1
SCLK SMBus
OUT0 23 OUT3
OUT1# 6
SDA Controller
OUT0# 22 OUT3#
7
OUT2
OUT2# OE_0 21 OE_3
8
PLL/BYPASS#
OUT1 20 OUT2
9
OUT3
SRC
OUT3#
OUT1# 19 OUT2#
10
SRC#
V 18 V
DD 11 DD
PLL/BYPASS# 17 PLL_BW#
12
SCLK 16 SRC_STOP#
13
DIV
PLL_BW# SDA 15 PWRDWN#
14
PLL
www.pericom.com 03/27/13
14-0195
1PI6C20400A
1:4 Clock Driver for Intel PCIe Chipsets
Pin Descriptions
Type Pin No Description
Pin Name
SRC & SRC# Input 2, 3 0.7V Differential SRC input from PI6C410 clock synthesizer
3.3V LVTTL input for enabling outputs, active high.
OE_0 & OE_3 Input 8, 21 OE_0 for OUT0 / OUT0#
OE_3 for OUT3 / OUT3#
3.3V LVTTL input for inverting the OE, SRC_STOP# and
PWRDWN# pins.
OE_INV Input 25
When 0 = same stage
When 1 = OE_0, OE_3, SRC_STOP#, PWRDWN# inverted.
6, 7, 9, 10, 19, 20,
OUT[0:3] & OUT[0:3]# Output 0.7V Differential outputs
22, 23
PLL/BYPASS# Input 12 3.3V LVTTL input for selecting fan-out of PLL operation.
SCLK Input 13 SMBus compatible SCLOCK input
SDA I/O 14 SMBus compatible SDATA
IREF Input 26 External resistor connection to set the differential output current
SRC_STOP# Input 16 3.3V LVTTL input for SRC stop, active low
PLL_BW# Input 17 3.3V LVTTL input for selecting the PLL bandwidth
PWRDWN# Input 15 3.3V LVTTL input for Power Down operation, active low
V Power 1, 5, 11, 18, 24 3.3V Power Supply for Outputs
DD
VSS Ground 4 Ground for Outputs
VSS_A Ground 27 Ground for PLL
VDD_A Power 28 3.3V Power Supply for PLL
Serial Data Interface (SMBus)
This part is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit
address and read/write bit as shown below.
Address Assignment
A6 A5 A4 A3 A2 A1 A0 W/R
1 1 0 1 1 1 0 0/1
Data Protocol
1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit
Byte Data
Start Slave Register Data Stop
R/W Ack Ack Count Ack Ack Byte N Ack
bit Addr offset Byte 0 bit
= N - 1
Notes:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
www.pericom.com 03/27/13
14-0195
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