A product Line of Diodes Incorporated PI6C20400B 1:4 Clock Driver for Intel PCIe 3.0 Chipsets Description Features e PTh I6C20400B is a PCIe 3.0 compliant high-speed, low-noise Phase jitter filter for PCIe 3.0 application differential clock buffer designed to be companion to PCIe 3.0 Four Pairs of Differential Clocks clock generator. It is backward compatible with PCIe 1.0 and 2.0 Low skew < 50ps specicfi ation. Low jitter < 50ps cycle-to-cycle < 1 ps additive RMS phase jitter e dTh evice distributes the differential SRC clock from PCIe 3.0 clock generator to four differential pairs of clock outputs either Output Enable for all outputs with or without PLL. The clock outputs are controlled by input Outputs tristate control via SMBus selection of SRC STOP , PWRDWN and SMBus, SCLK and Programmable PLL Bandwidth SDA. When input of either SRC STOP or PWRDWN is low, the output clocks are Tristated. When PWRDWN is low, the 100 MHz PLL Mode operation SDA and SCLK inputs must be Tri-stated. 100 - 400 MHz Bypass Mode operation 3.3V Operation Packaging (Pb-free and Green): -28-Pin SSOP (H28) -28-Pin TSSOP (L28) Block Diagram Pin Configuration OE INV OE 0 & OE 3 Output V 1 28 V DD DD A SRC STOP Control 27 SRC 2 V SS A PWRDWN OUT0 SRC 26 I 3 REF OUT0 V 4 25 OE INV SS OUT1 24 VDD 5 VDD SCLK SMBus OUT1 OUT0 6 23 OUT3 Controller SDA 22 OUT2 OUT0 7 OUT3 OUT2 OE 0 21 OE 3 8 PLL/BYPASS OUT1 9 20 OUT2 OUT3 SRC 19 OUT3 OUT1 10 OUT2 SRC V 18 V DD 11 DD PLL/BYPASS 12 17 PLL BW 16 SCLK 13 SRC STOP DIV SDA 15 PWRDWN 14 PLL BW PLL All trademarks are property of their respective owners. www.diodes.com 01/06/17 17-0006 1A product Line of Diodes Incorporated PI6C20400B Pinout Table Pin Pin Name Type Description 2, 3 SRC & SRC Input 0.7V Differential SRC input from PI6C410 clock synthesizer 3.3V LVTTL input for enabling outputs, active high. 8, 21 OE 0 & OE 3 Input OE 0 for OUT0 / OUT0 OE 3 for OUT3 / OUT3 3.3V LVTTL input for inverting the OE, SRC STOP and PWRDWN pins. 25 OE INV Input When 0 = same stage When 1 = OE 0, OE 3, SRC STOP , PWRDWN inverted. 6, 7, 9, 10, 19, OUT 0:3 & OUT 0:3 Output 0.7V Differential outputs 20, 22, 23 12 PLL/BYPASS Input 3.3V LVTTL input for selecting fan-out of PLL operation. 13 SCLK Input SMBus compatible SCLOCK input 14 SDA I/O SMBus compatible SDATA 26 IREF Input External resistor connection to set the differential output current 16 SRC STOP Input 3.3V LVTTL input for SRC stop, active low 17 PLL BW Input 3.3V LVTTL input for selecting the PLL bandwidth 15 PWRDWN Input 3.3V LVTTL input for Power Down operation, active low 1, 5, 11, 18, 24 V Power 3.3V Power Supply for Outputs DD 4 VSS Ground Ground for Outputs 27 VSS A Ground Ground for PLL 28 VDD A Power 3.3V Power Supply for PLL Serial Data Interface (SMBus) This part is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address Assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 1 1 0 0/1 Data Protocol 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit Byte Data Start Slave Register Data R/W Ack Ack Count Ack Ack Byte N Ack Stop bit bit Addr offset Byte 0 = N - 1 Notes: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. All trademarks are property of their respective owners. www.diodes.com 01/06/17 17-0006 2