A Product Line of Pb Diodes Incorporated Lead-free Green PI6C20400B 1:4 Clock Driver for Intel PCIe 3.0 Chipsets Description Features e PTh I6C20400B is a PCIe 3.0 compliant high-speed, low-noise Phase jitter filter for PCIe 3.0 application differential clock buffer designed to be companion to PCIe 3.0 Four Pairs of Differential Clocks clock generator. It is backward compatible with PCIe 1.0 and 2.0 Low skew < 50ps specicfi ation. Low jitter < 50ps cycle-to-cycle e dTh evice distributes the differential SRC clock from PCIe 3.0 < 1 ps additive RMS phase jitter clock generator to four differential pairs of clock outputs either Output Enable for all outputs with or without PLL. The clock outputs are controlled by input Outputs tristate control via SMBus selection of SRC STOP , PWRDWN and SMBus, SCLK and Programmable PLL Bandwidth SDA. When input of either SRC STOP or PWRDWN is low, the output clocks are Tristated. When PWRDWN is low, the 100 MHz PLL Mode operation SDA and SCLK inputs must be Tri-stated. 100 - 400 MHz Bypass Mode operation 3.3V Operation Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Block Diagram Halogen and Antimony Free. Green Device (Note 3) OE INV For automotive applications requiring specic cfi hange control OE 0 & OE 3 Output (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, SRC STOP Control PWRDWN and manufactured in IATF 16949 certified facilities), please OUT0 OUT0 contact us or your local Diodes representative. OUT1 A Product Line of Diodes Incorporated PI6C20400B Pin Configuration 28 V 1 V DD DD A SRC 27 V 2 SS A SRC 3 26 I REF 25 VSS 4 OE INV V 5 24 V DD DD OUT0 6 23 OUT3 22 OUT0 7 OUT3 OE 0 8 21 OE 3 20 OUT1 9 OUT2 OUT1 19 OUT2 10 V 11 18 V DD DD 17 PLL/BYPASS 12 PLL BW SCLK 16 SRC STOP 13 SDA 14 15 PWRDWN Pin Description Pin Pin Name Type Description 2, 3 SRC & SRC Input 0.7V Differential SRC input from PI6C410 clock synthesizer 3.3V LVTTL input for enabling outputs, active high. 8, 21 OE 0 & OE 3 Input OE 0 for OUT0 / OUT0 OE 3 for OUT3 / OUT3 3.3V LVTTL input for inverting the OE, SRC STOP and PWRDWN pins. 25 OE INV Input When 0 = same stage When 1 = OE 0, OE 3, SRC STOP , PWRDWN inverted. 6, 7, 9, 10, 19, OUT 0:3 & OUT 0:3 Output 0.7V Differential outputs 20, 22, 23 12 PLL/BYPASS Input 3.3V LVTTL input for selecting fan-out of PLL operation. 13 SCLK Input SMBus compatible SCLOCK input 14 SDA I/O SMBus compatible SDATA 26 IREF Input External resistor connection to set the differential output current 16 SRC STOP Input 3.3V LVTTL input for SRC stop, active low 17 PLL BW Input 3.3V LVTTL input for selecting the PLL bandwidth 15 PWRDWN Input 3.3V LVTTL input for Power Down operation, active low 1, 5, 11, 18, 24 V Power 3.3V Power Supply for Outputs DD 4 VSS Ground Ground for Outputs 27 VSS A Ground Ground for PLL 28 VDD A Power 3.3V Power Supply for PLL www.diodes.com January 2021 PI6C20400B 2 Diodes Incorporated Document Number DS43443 Rev 1-2