PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets Features Description Four Pairs of Differential Clocks Pericom Semiconductor s PI6C20400 is a high-speed, low-noise differential clock buffer designed to be companion to PI6C410B. Low skew < 50ps The device distributes the differential SRC clock from PI6C410B Low jitter < 50ps to four differential pairs of clock outputs either with or without Output Enable for all outputs PLL. The clock outputs are controlled by input selection of SRC STOP , PWRDWN and SMBus, SCLK and SDA. When Outputs tristate control via SMBus input of either SRC STOP or PWRDWN is low, the output Power Management Control clocks are Tristated. When PWRDWN is low, the SDA and Programmable PLL Bandwidth SCLK inputs must be Tri-stated. PLL or Fanout operation 3.3V Operation Packaging (Pb-free and Green): 28-Pin SSOP (H28) & 28-Pin TSSOP (L28) Block Diagram Pin Configuration 28 OE INV V 1 V DD DD A OE 0 & OE 3 Output SRC 2 27 V SS A SRC STOP Control PWRDWN SCR 3 26 I REF OUT0 OUT0 V 25 OE INV SS 4 OUT0 V 24 V SMBus 5 SCLK DD DD OUT1 Controller SDA OUT0 23 OUT3 6 OUT2 22 OUT2 OUT0 7 OUT3 PLL/BYPASS 21 OUT3 OE 0 8 OE 3 SRC OUT3 20 OUT1 9 OUT2 SRC 19 OUT1 10 OUT2 18 V 11 V DD DD DIV 17 PLL/BYPASS 12 PLL BW PLL BW PLL SCLK 13 16 SRC STOP SDA 14 15 PWRDWN www.pericom.com 03/26/13 14-0197 1PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets Pin Descriptions Type Pin No Description Pin Name SRC & SRC Input 2, 3 0.7V Differential SRC input from PI6C410 clock synthesizer 3.3V LVTTL input for enabling outputs, active high. OE 0 & OE 3 Input 8, 21 OE 0 for OUT0 / OUT0 OE 3 for OUT3 / OUT3 3.3V LVTTL input for inverting the OE, SRC STOP and PWRDWN pins. OE INV Input 25 When 0 = same stage When 1 = OE 0, OE 3, SRC STOP , PWRDWN inverted. 6, 7, 9, 10, 19, 20, OUT 0:3 & OUT 0:3 Output 0.7V Differential outputs 22, 23 PLL/BYPASS Input 12 3.3V LVTTL input for selecting fan-out of PLL operation. SCLK Input 13 SMBus compatible SCLOCK input SDA I/O 14 SMBus compatible SDATA IREF Input 26 External resistor connection to set the differential output current SRC STOP Input 16 3.3V LVTTL input for SRC stop, active low PLL BW Input 17 3.3V LVTTL input for selecting the PLL bandwidth PWRDWN Input 15 3.3V LVTTL input for Power Down operation, active low V Power 1, 5, 11, 18, 24 3.3V Power Supply for Outputs DD VSS Ground 4 Ground for Outputs VSS A Ground 27 Ground for PLL VDD A Power 28 3.3V Power Supply for PLL Serial Data Interface (SMBus) This part is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 1 1 0 0/1 Data Protocol 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit Byte Data Start Slave Register Data Stop R/W Ack Ack Count Ack Ack Byte N Ack bit Addr offset Byte 0 bit = N - 1 Notes: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. 14-0197 2 www.pericom.com 03/26/13