A Product Line of Pb Diodes Incorporated Lead-free Green PI6C20400 1:4 Clock Driver for Intel PCI Express Chipsets Features Description Four Pairs of Differential Clocks e PTh I6C20400 is a high-speed, low-noise differential clock buffer designed to be companion to PI6C410B. The device distributes Low skew < 50ps the differential SRC clock from PI6C410B to four differential pairs Low jitter < 50ps of clock outputs either with or without PLL. The clock outputs Output Enable for all outputs are controlled by input selection of SRC STOP , PWRDWN Outputs tristate control via SMBus and SMBus, SCLK and SDA. When input of either SRC STOP Power Management Control or PWRDWN is low, the output clocks are Tristated. When Programmable PLL Bandwidth PWRDWN is low, the SDA and SCLK inputs must be Tri-stated. PLL or Fanout operation 3.3V Operation Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Block Diagram Halogen and Antimony Free. Green Device (Note 3) For automotive applications requiring specific change control OE INV (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and OE 0 & OE 3 Output manufactured in IATF 16949 certified facilities), please contact SRC STOP Control us or your local Diodes representative. PWRDWN OUT0 OUT0 A Product Line of Diodes Incorporated PI6C20400 Pin Configuration 28 V 1 V DD DD A SRC 27 V 2 SS A 26 SCR 3 I REF V 25 OE INV SS 4 24 V 5 V DD DD OUT0 23 OUT3 6 22 OUT0 7 OUT3 OE 0 21 OE 3 8 OUT1 9 20 OUT2 19 OUT1 10 OUT2 V 11 18 V DD DD 17 PLL/BYPASS 12 PLL BW SCLK 13 16 SRC STOP 15 SDA 14 PWRDWN Pin Descriptions Pin Pin Name Type Description 2, 3 SRC & SRC Input 0.7V Differential SRC input from PI6C410 clock synthesizer 3.3V LVTTL input for enabling outputs, active high. 8, 21 OE 0 & OE 3 Input OE 0 for OUT0 / OUT0 OE 3 for OUT3 / OUT3 3.3V LVTTL input for inverting the OE, SRC STOP and PWRDWN pins. 25 OE INV Input When 0 = same stage When 1 = OE 0, OE 3, SRC STOP , PWRDWN inverted. 6, 7, 9, 10, 19, OUT 0:3 & OUT 0:3 Output 0.7V Differential outputs 20, 22, 23 12 PLL/BYPASS Input 3.3V LVTTL input for selecting fan-out of PLL operation. 13 SCLK Input SMBus compatible SCLOCK input 14 SDA I/O SMBus compatible SDATA 26 IREF Input External resistor connection to set the differential output current 16 SRC STOP Input 3.3V LVTTL input for SRC stop, active low 17 PLL BW Input 3.3V LVTTL input for selecting the PLL bandwidth 15 PWRDWN Input 3.3V LVTTL input for Power Down operation, active low 1, 5, 11, 18, 24 V Power 3.3V Power Supply for Outputs DD 4 VSS Ground Ground for Outputs 27 VSS A Ground Ground for PLL 28 VDD A Power 3.3V Power Supply for PLL www.diodes.com January 2021 PI6C20400 2 Diodes Incorporated Document Number DS43191 Rev 1-2