PI6C20800B PCI Express 3.0 1:8 HCSL Clock Buffer Features Description Phase jitter filter for PCIe 3.0 application PI6C20800B is a PCIe 3.0 compliant, high-speed, low-noise differential clock buffer designed to be a companion to PCI Eight Pairs of Differential Clocks Express 3.0 clock generator for Intel server chipsets. The device Low skew < 50ps (PI6C20800B), <60ps (PI6C20800BI) distributes the differential SRC clock from PCIe clock generator Low Cycle-to-cycle jitter < 60ps to eight differential pairs of clock outputs either with or without PLL. The input SRC clock can be divided by 2 when SRC DIV Output Enable for all outputs is LOW. The clock outputs are controlled by input selection of Outputs Tristate control via SMBus SRC STOP , PWRDWN and SMBus, SCLK and SDA. When Power Management Control input of either SRC STOP or PWRDWN is LOW, the output clocks are Tristated. When PWRDWN is LOW, the SDA and Programmable PLL Bandwidth SCLK inputs must be Tristated. PLL or Fanout operation 3.3V Operation Industrial Temperature Option - PI6C20800BI Packaging (Pb-Free & Green): 48-Pin TSSOP (A) Block Diagram Pin Configuration (48-Pin TSSOP) OE INV 1 48 SRC DIV V DD A OE 0:7 Output V 2 47 V DD SS A SRC STOP Control 3 46 VSS IREF OUT0 PWRDWN SRC 4 45 LOCK OUT0 5 44 SRC OE 7 OUT1 43 OE 0 6 OE 4 OUT1 SCLK SMBus OE 3 7 42 OUT7 SDA Controller 8 41 OUT0 OUT7 OUT2 OUT0 9 40 OE INV OUT2 10 39 VSS VDD PLL/BYPASS OUT3 V 11 38 OUT6 DD OUT3 12 37 SRC DIV OUT1 OUT6 OUT4 OUT1 13 36 OE 6 SRC OUT4 OE 1 14 35 OE 5 SRC 34 OE 2 15 OUT5 OUT5 OUT2 16 33 OUT5 OUT5 17 32 OUT2 VSS OUT6 V 18 31 V SS DD OUT6 DIV 19 30 VDD OUT4 PLL BW PLL OUT3 20 29 OUT4 OUT7 OUT3 21 28 PLL BW OUT7 PLL/BYPASS 22 27 SRC STOP SCLK 23 26 PWRDWN LOCK 25 SDA 24 VSS www.pericom.com P-0.1 03/27/13 14-0189 1PI6C20800B PCI Express 3.0 1:8 HCSL Clock Buffer Pinout Table Pin Name Type Pin Descriptions 3.3V LVTTL input for selecting input frequency divide by 2, active SRC DIV Input 1 LOW. SRC & SRC Input 4, 5 0.7V Differential SRC input from PI6C410 clock synthesizer 6, 7, 14, 15, 35, 36, OE 0:7 Input 3.3V LVTTL input for enabling outputs, active HIGH. 43, 44 3.3V LVTTL input for inverting the OE, SRC STOP and PWRDWN pins. OE INV Input 40 When 0 = same stage When 1 = OE 0:7 , SRC STOP , PWRDWN inverted. 8, 9, 12, 13, 16 17, 20, OUT 0:7 & OUT 0:7 Output 21, 29, 30, 33, 34, 37, 0.7V Differential outputs 38, 41, 42 PLL/BYPASS Input 22 3.3V LVTTL input for selecting fan-out of PLL operation. SCLK Input 23 SMBus compatible SCLOCK input SDA I/O 24 SMBus compatible SDATA I Input 46 External resistor connection to set the differential output current REF SRC STOP Input 27 3.3V LVTTL input for SRC stop, active LOW PLL BW Input 28 3.3V LVTTL input for selecting the PLL bandwidth PWRDWN Input 26 3.3V LVTTL input for Power Down operation, active LOW 3.3V LVTTL output, transition high when PLL lock is achieved LOCK Output 45 (Latched output) V Power 2, 11, 19, 31, 39 3.3V Power Supply for Outputs DD V Ground 3, 10, 18, 25, 32 Ground for Outputs SS V Ground 47 Ground for PLL SS A V Power 48 3.3V Power Supply for PLL DD A Serial Data Interface (SMBus) This part is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 1 1 0 0/1 Data Write Protocol(1) 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit Data Data Start Register Byte Count Slave Addr W Ack Ack Ack Byte Ack Byte N Ack Stop bit bit offset = N Offset - 1 Note: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. www.pericom.com P-0.1 03/27/13 14-0189 2