PI6C20800S PCI Express 1:8 HCSL Clock Buffer Features Description PI6C20800S is a PCI Express, high-speed, low-noise differential Phase jitter filter for PCIe application clock buffer designed to be a companion to PI6C410BS PCI Eight Pairs of Differential Clocks Express clock generator for Intel server chipsets. The device Low skew < 50ps (PI6C20800S), <60ps (PI6C20800SI) distributes the differential SRC clock from PI6C410BS to eight differential pairs of clock outputs either with or without PLL. Low Cycle-to-cycle jitter < 70ps The input SRC clock can be divided by 2 when SRC DIV is Output Enable for all outputs LOW. The clock outputs are controlled by input selection of Outputs Tristate control via SMBus SRC STOP , PWRDWN and SMBus, SCLK and SDA. When Power Management Control input of either SRC STOP or PWRDWN is LOW, the output clocks are Tristated. When PWRDWN is LOW, the SDA and Programmable PLL Bandwidth SCLK inputs must be Tristated. PLL or Fanout operation 3.3V Operation Industrial Temperature Option - PI6C20800SI Packaging (Pb-Free & Green): 48-Pin SSOP (V) 48-Pin TSSOP (A) Block Diagram Pin Configuration 48 SRC DIV 1 V DD A 47 V 2 V DD SS A 46 V 3 I OE INV SS REF OE 0:7 Output 45 SRC 4 LOCK SRC STOP Control 44 SRC 5 OE 7 OUT0 PWRDWN OUT0 43 OE 0 6 OE 4 42 OE 3 7 OUT7 OUT1 OUT1 SCLK 41 SMBus OUT0 8 OUT7 SDA Controller 40 OUT2 OUT0 9 OE INV OUT2 39 VSS 10 V DD PLL/BYPASS OUT3 38 V 11 OUT6 DD OUT3 37 OUT1 12 OUT6 SRC DIV OUT4 36 OUT1 13 OE 6 SRC OUT4 35 OE 1 14 OE 5 SRC OUT5 34 OE 2 15 OUT5 OUT5 33 OUT2 16 OUT5 OUT6 32 OUT2 17 V SS OUT6 DIV 31 PLL BW V 18 V SS DD PLL OUT7 30 V 19 OUT4 DD OUT7 29 OUT3 20 OUT4 LOCK 28 OUT3 21 PLL BW 27 PLL/BYPASS 22 SRC STOP 26 SCLK 23 PWRDWN 25 SDA 24 V SS 14-0190 1 www.pericom.com 03/27/13 PI6C20800S PCI Express 1:8 HCSL Clock Buffer Pin Descriptions Type Pin Descriptions Pin Name 3.3V LVTTL input for selecting input frequency divide by 2, SRC DIV Input 1 active LOW. SRC & SRC Input 4, 5 0.7V Differential SRC input from PI6C410 clock synthesizer 6, 7, 14, 15, 35, 36, OE 0:7 Input 3.3V LVTTL input for enabling outputs, active HIGH. 43, 44 3.3V LVTTL input for inverting the OE, SRC STOP and PWRDWN pins. OE INV Input 40 When 0 = same stage When 1 = OE 0:7 , SRC STOP , PWRDWN inverted. 8, 9, 12, 13, 16 17, OUT 0:7 & OUT 0:7 Output 20, 21, 29, 30, 33, 34, 0.7V Differential outputs 37, 38, 41, 42 PLL/BYPASS Input 22 3.3V LVTTL input for selecting fan-out of PLL operation. SCLK Input 23 SMBus compatible SCLOCK input SDA I/O 24 SMBus compatible SDATA I Input 46 External resistor connection to set the differential output current REF SRC STOP Input 27 3.3V LVTTL input for SRC stop, active LOW PLL BW Input 28 3.3V LVTTL input for selecting the PLL bandwidth PWRDWN Input 26 3.3V LVTTL input for Power Down operation, active LOW 3.3V LVTTL output, transition high when PLL lock is achieved LOCK Output 45 (Latched output) V Power 2, 11, 19, 31, 39 3.3V Power Supply for Outputs DD V Ground 3, 10, 18, 25, 32 Ground for Outputs SS V Ground 47 Ground for PLL SS A V Power 48 3.3V Power Supply for PLL DD A Serial Data Interface (SMBus) This part is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 1 1 0 0/1 (1) Data Write Protocol 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit Byte Data Data Start Slave Register W Ack Ack Count Ack Byte Ack Byte N Ack Stop bit bit Addr offset = N Offset - 1 Note: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. 14-0190 2 www.pericom.com 03/27/13