PI6C2409-1H Zero-Delay Clock Buffer Features Description The PI6C2409-1H is a PLL based, zero-delay buffer, with the ability Maximum rated frequency: 133 MHz t o d i s t r i b u t e n i n e o u t p u t s o f u p t o 1 3 3 M H z a t 3 . 3 V. Low cycle-to-cycle jitter All the outputs are distributed from a single clock input CLKIN and Input to output delay, less than 200ps output OUT0 performs zero delay by connecting a feedback to PLL. Internal feedback allows outputs to be synchronized to the PI6C2409-1H has two banks of four outputs that can be controlled by clock input the selection inputs, SEL1 & SEL2. It also has a power sparing feature: Operates at 3.3V V DD when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all Space-saving Package: (Pb-free & Green available) outputs are referenced from CLKIN. PI6C2409-1H is available in - 16-Pin TSSOP (L) high drive and industrial environment versions. - 16-Pin SOIC (W) A n i n t e r n a l f e e d b a c k o n O U T 0 i s u s e d t o s y n c h r o n i z e t h e outputs to the input the relationship between loading of this signal a n d t h e o u t p u t s d e t e r m i n e s t h e i n p u t - o u t p u t d e l a y . P I 6 C 2 4 0 9 - 1 H a r e c h a r a c t e r i z e d f o r b o t h c o m m e r c i a l a n d industrial operation Block Diagram Pin Configuration OUT0 CLKIN 16 1 OUT0 PLL MUX OUTA1 CLKIN 15 OUTA4 OUTA1 2 OUTA2 OUTA2 14 3 OUTA3 OUTA3 13 VDD 4 16-Pin V DD SEL1 Decode OUTA4 W, L GND 5 12 GND Logic SEL2 OUTB1 11 6 OUTB4 OUTB1 OUTB2 7 10 OUTB3 OUTB2 OUTB3 9 SEL2 8 SEL1 PI6C2409-1H OUTB4 05/26/11 10-0252 1PI6C2409-1H Zero-Delay Clock Buffer Input Select Decoding SEL2 SEL1 OUTA 1-4 OUTB 1-4 Output Source PLL (OUT0) 0 0 3-State 3-State PLL ON 0 1 PLL 3-State PLL ON 1 0 CLKIN CLKIN CLKIN OFF 1 1 PLL PLL PLL ON Pin Description Pin Signal Description 1 CLKIN Input clock reference frequency (weak pull-down) 2, 3, 14, 15 OUTA 1-4 Clock outputs, Bank A 4, 13 VDD 3.3V supply 5, 12 GND Ground 6, 7, 10 ,11 OUTB 1-4 Clock outputs, Bank B 8 SEL2 Select input, bit 2 (weak pull-up) 9 SEL1 Select input, bit 1 (weak pull-up) 16 OUT0 Clock Output , internal PLL feedback 05/26/11 10-0252 2