PI6C2510-133E Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs Features Description Operating Frequency up to 150 MHz The PI6C2510-133E is a enhanced, low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency Low-Noise Phase-Locked Loop Clock Distribution that meets clock signals for SDRAM and server applications. By connecting 133 MHz Registered DIMM Synchronous DRAM modules the feedback FB OUT output to the feedback FB IN input, the for server/workstation/PC applications propagation delay from the CLK IN input to any clock output Allows Clock Input to have Spread Spectrum modulation for will be nearly zero. This zero-delay feature allows the CLK IN EMI reduction input clock to be distributed, providing one clock input to one Low jitter: Cycle-to-Cycle jitter 75ps max. bank of ten outputs, with an output enable. On-chip series damping resistor at clock output drivers for This clock driver is designed to meet the PC133 SDRAM low noise and EMI reduction Registered DIMM speci cation. For test purposes, the PLL can Operates at 3.3V VCC, 085C be bypassed by strapping AVCC to ground. Packages (Pb-free & Green available): Plastic 24-pin TSSOP (L) Block Diagram Pin Con guration AGND 1 24 CLK IN V 2 23 AV CC CC Y0 3 22 V G CC Y1 4 21 Y9 10 Y 0:9 Y2 5 20 Y8 24-Pin GND 6 19 GND L CLK IN GND 7 18 GND FB OUT PLL Y3 8 17 Y7 FB IN Y4 9 16 Y6 V 10 15 Y5 AVcc CC G 11 14 V CC FB OUT 12 13 FB IN Functional Table Inputs Outputs G Y 0:9 FB OUT L L CLK IN H CLK IN CLK IN PS8505B 11/18/09 09-0006 1PI6C2510-133E Lownoise, Phase Locked Loop Clock Driver with 10 Clock Outputs Pin Functions Pin Pin Type Description Name Number CLK IN 24 I Reference Clock input. CLK IN allows spread spectrum. FB IN 13 I Feedback input. FB IN provides the feedback signal to the internal PLL. Output bank enable. When G is LOW, outputs Y 0:9 are disabled to a logic G11 I low state. When G is HIGH, all outputs Y 0:9 are enabled. Feedback output. FB OUT is dedicated for external feedback. FB OUT 12 O FB OUT has an embedded series-damping resistor of same value as clock outputs Y 0:9 . 3, 4, 5, 8, 9, 15, 16, Clock outputs. These outputs provide low-skew copies of CLK IN. Y 0:9 O 17, 20, Each output has an embedded series-damping resistor. 21 Analog power supply. AVcc can be also used to bupass the PLL for test AV 23 Power purposes. When AVcc is strapped to ground, PLL is bypassed and CLK IN CC bufferef directly to the device outputs. Analog ground. AGND provides thr ground referencefor the analog cir- AGND 1 Ground cuitry/ 2, 10, 14, V Power Power Supply CC 22 6, 7, 18, GND Ground Ground 19 DC Speci cations - Absolute maximum ratings over operating free-air temperature range. Symbol Parameter Min. Max. Units V Input voltage range I V + 0.5 CC V Output voltage range O 0.5 V V DC DC input voltage +5.0 I I DC DC output current 100 mA O Maximum power dissipation at TA = 59C in Power 1.0 W still airr T Storage temperature 65 160 C STG Note: Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. Parameter Test Conditions VCC Min Typ Max Units I V = V or GND I = 0 3.6V 10 uA CC I CC O C V = V or GND 4 I I CC 3.3V pF C V = V or GND 6 O O CC PS8505B 11/18/09 09-0006 2