PI6C3991 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock Features Description All output pair skew <100ps typical (250 Max.) PI6C3991 offers selectable control over system clock functions. These multiple-output clock drivers provide the system integrator 3.75 MHz to 80 MHz output operation with functions necessary to optimize the timing of high-perfor- User-selectable output functions mance computer systems. Eight individual drivers, arranged as four Selectable skew to 18ns pairs of user-controllable outputs, can each drive terminated trans- mission lines with impedances as low as 50 ohms while delivering Inverted and Non-Inverted minimal and specified output skews and full-swing logic levels Operation at and input frequency (LVTTL). Operation at 2X and 4X input frequency Each output can be hardwired to one of nine skews or function (input as low as 3.75 MHz, x4 operation) configurations. Delay increments of 0.7ns to 1.5ns are determined Zero input-to-output delay by the operating frequency with outputs able to skew up to 6 time units from their nominal zero skew position. The completely 50% duty-cycle outputs integrated PLL allows external load and transmission line delay LVTTL outputs drive 50-ohm terminated lines effects to be canceled. The user can create output-to-output skew Operates from a single 3.3V supply up to 12 time units. Low operating current Divide-by-two and divide-by-four output functions are provided Available in 32-pin PLCC (J) package for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow Jitter < 200ps peak-to-peak (< 25ps RMS) distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature allows flexibility and simplifies system timing distribution design for complex high-speed systems. Logic Block Diagram Pin Configuration Test Phase FB VCO and Freq. Filter Time Unit REF DET 4321 32 31 30 Generator 5 29 3F1 2F0 FS 6 28 4F0 GND 4Q0 7 27 4F1 1F1 4F0 8 26 4F1 V 1F0 CCQ 4Q1 32-Pin Select Inputs V 9 25 V CCN CCN (three level) Skew J 3Q0 4Q1 10 24 3F0 1Q0 3F1 4Q0 11 23 1Q1 3Q1 Select 12 22 GND GND 2Q0 13 21 2F0 GND GND Matrix 14 15 16 17 18 19 20 2F1 2Q1 1Q0 1F0 1F1 1Q1 PS8450D 03/06/08 1 3Q1 3F0 3Q0 FS V V CCN CCQ FB REF V GND CCN 2Q1 TEST 2Q0 2F1PI6C3991 3.3V High-Speed, Low-Voltage Programmable 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901Skew Clock Buffer - SuperClock2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Pin Descriptions SOignal NameIn/ Descriptio RIEF Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured. FIB PLL feedback input (typically connected to one of the eight outputs) FIS Three-level frequency range select. see Table 1. 1IF0, 1F1 Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2. 2IF0, 2F1 Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2. 3IF0, 3F1 Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2. 4IF0, 4F1 Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2. TIEST Three-level select. See test mode section under the block diagram descriptions 1OQ0, 1Q1 Output pair 1. See Table2 2OQ0, 2Q1 Output pair 2. See Table2 3OQ0, 3Q1 Output pair 3. See Table2 4OQ0, 4Q1 Output pair 4. See Table2 VPsWR Power supply for output driver CCN VPyWR Power supply for internal circuitr CCQ GRND PdW Groun (1) (1) Table 1. Frequency Range Select and t Calculation Table 2. Programmable Skew Configurations U 1 Fsunction Selects Output Function t = Approximate F (MHz) U NOM f N (1,2) NOM FS Freq. (MHz) at 1F1, 2F1, 1F0, 2F0, 1Q0, 1Q1, 31Q0, 3Q1 4Q0, 4Q where N= which t = 1.0ns 3F1, 4F1 3F0, 4F0 2Q0, 2Q1 U M.in. Max LWOW LtO 4D2ivide by 2 Divide by U L5OW 10344722. LDOW MtI 3 6t 6t U U U M5ID 20562538. LHOW HtIG 2 4t 4t U U U H0IGH 40861562. MWID LtO 1 2t 2t U U U MDID MtI 0 0t 0t U U U MHID HtIG +1 +2t +2t U U U HWIGHLtO +2 +4t +4t U U U HDIGH MtI +3 +6t +6t U U U HHIGHHtIG +4Ddivide by 4 Inverte U Notes: 1. For all three-state inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an CC open connection. Internal termination circuitry holds an unconnected input to V /2. CC 2. The level to be set on FS is determined by the normal operating frequency (f ) and Time Unit Generator NOM (see Logic Block Diagram). Nominal frequency (f ) always appears at 1Q0 and the other outputs when they are operated in NOM their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be f when the output connected NOM to FB is undivided. The frequency of the REF and FB inputs will be f /2 or f /4 when the part is configured for a frequency NOM NOM multiplication by using a divided output as the FB input. PS8450D 11/12/08 2