PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Features Description Pin-to-pin compatible to ICS8533-01 The PI6C48533-01 is a high-performance low-skew LVPECL fanout Maximum operation frequency: 800MHz buffer. PI6C48533-01 features two selectable differential inputs and translates to four LVPECL ultra-low jitter outputs. The inputs can 4 pair of differential LVPECL outputs also be configured to single-ended with external resistor bias circuit. Selectable differential CLK and PCLK inputs The CLK input accepts LPECL or LVDS or LVHSTL or SSTL or CLK, CLK pair accepts LVDS, LVPECL, LVHSTL, n HCSL signals, and PCLK input accepts LVPECL or SSTL or CML SSTL and HCSL input level signals. The outputs are synchronized with input clock during asyn- PCLK, nPCLK pair supports LVPECL, CML and SSTL chronous assertion/deassertion of CLK EN pin. PI6C48533-01 is input level ideal for differential to LVPECL translations and/or LVPECL clock distribution. Typical clock translation and distribution applications Output Skew: 100ps (maximum) are data-communications and telecommunications. Part-to-part skew: 150ps (maximum) Propagation delay: 2ns (maximum) 3.3V power supply o o Operating Temperature: -40 C to 85 C Packaging (Pb-free & Green avaliable): -20-pin TSSOP (L) Block Diagram Pin Diagram CLK EN D Q V EE 1 20 Q 0 LE CLK EN 2 19 Q n 0 CLK CLK SEL 3 18 V CC 0 CLK Q n 0 CLK 4 17 Q 1 Q PCLK n 0 CLK 1 n 5 16 Q n 1 PCLK n Q 1 PCLK 6 15 Q 2 Q n 1 PCLK 7 n 14 Q n 2 NC 8 13 V CC Q 2 CLK SEL NC 9 Q 12 Q n 2 3 V CC 10 11 Q n 3 Q 3 Q n 3 Rev B 6/23/2015 1 15-0084PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Pin Description Name Pin Type Description V 1 P Connect to Negative power supply EE Synchronizing clock enable. When high, clock outputs follow clock input. When low, Q x CLK EN 2 I PU outputs are forced low, Q outputs are forced high. LVCMOS/LVTTL level with 50K pull-up. n x CLK Clock select input. When high, selects PCLK input. When low, selects CLK input. LVCMOS/ 3 I PD SEL LVTTL level with 50K pull-down. CLK 4 I PD Non-inverting differential clock input CLK 5 I PU Inverting differential clock input n PCLK 6 I PD Non-inverting differential clock input PCLK 7 I PU Inverting differential clock input n NC 8, 9 Not connected 10, 13, V P Connect to 3.3V. CC 18 Q 11, n 3, O Differential output pair, LVPECL interface level. Q 12 3 Q 14, n 2, O Differential output pair, LVPECL interface level. Q 15 2 Q 16, n 1, O Differential output pair, LVPECL interface level. Q 17 1 Q , 19, n 0 O Differential output pair, LVPECL interface level. Q 20 0 Note: 1. I = Input, O = Output, P = Power supply connection, I PD = Input with pull down, I PU = Input with pull up Pin Characteristics Symbol Parameter Conditions Min. Typ. Max. Units C Input Capacitance 4 pF IN R pullup Input Pullup Resistance 50 K R pulldown Input Pulldown Resistance 50 (1) Control Input Function Table Inputs Outputs CLK EN CLK SEL Selected Source Q :Q Q : Q 0 3 n 0 n 3 0 0 CLK, CLK Diasbled: Low Diasbled: High n 0 1 PCLK, PCLK Disabled: Low Disabled: High n 1 0 CLK, CLK Enabled Enabled n 1 1 PCLK, PCLK Enabled Enabled n Note: 1. After CLK EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below. Rev B 6/23/2015 2 15-0084