PI6C48535-01 3.3V Low Skew 1-to-4 LVTTL/LVCMOS to LVPECL Fanout Buffer Features Description Maximum operation frequency: 500 MHz The PI6C48535-01 is a high-performance low-skew LVPECL fanout buffer. PI6C48535-01 features two selectable single-ended 4 pair of differential LVPECL outputs clock inputs and translates to four LVPECL outputs. The CLK 0 Selectable CLK and CLK inputs 0 1 and CLK inputs accept LVCMOS or LVTTL signals. The outputs 1 CLK , CLK accept LVCMOS, LVTTL input level 0 1 are synchronized with input clock during asynchronous assertion/ Output Skew: 80ps (maximum) deassertion of CLK EN pin. PI6C48535-01 is ideal for single- ended LVTTL/LVCMOS to LVPECL translations. Typical clock Part-to-part skew: 150ps (maximum) translation and distribution applications are data-communications Propagation delay: 1.9ns (maximum) and telecommunications. 3.3V power supply Additive jitter of 36.7fs (typical) o o Operating Temperature: -40 C to 85 C Packaging (Pb-free & Green available): 20-pin TSSOP (L) Block Diagram Pin Configuration D CLK EN Q 1 Q V 20 0 EE LE CLK EN 2 19 NQ 0 V CLK SEL 3 18 CC CLK 0 4 Q Q CLK 17 1 0 0 Q n 0 NC 5 16 NQ 1 CLK 1 1 Q CLK 6 15 2 1 Q 1 7 NQ NC 14 2 Q n 1 NC 8 V 13 CC Q NC 9 12 3 Q 2 CLK SEL 10 NQ Q V 11 3 n 2 CC Q 3 Q n 3 PS8735A 03/25/11 1 11-0040PI6C48535-01 3.3V Low Skew 1-to-4 LVTTL/LVCMOS to LVPECL Fanout Buffer Pin Description Name Pin Type Description V 1 P Connect to Negative power supply EE Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx CLK EN 2 I PU outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 50K pull up. Clock select input. When high, selects CLK input. When low, selects CLK input. 1 0 CLK SEL 3 I PD LVCMOS/LVTTL level with 50K pull down. CLK 4 I PD LVCMOS / LVTTL clock input 0 CLK 6 I PD LVCMOS / LVTTL clock input 1 NC 5, 7, 8, 9 No internal connection. 10, 13, V P Connect to 3.3V. CC 18 Q , Q 11, 12 O Differential output pair, LVPECL interface level. 3 n 3 Q , Q 14, 15 O Differential output pair, LVPECL interface level. 2 n 2 Q , Q 16, 17 O Differential output pair, LVPECL interface level. 1 n 1 Q , Q 19, 20 O Differential output pair, LVPECL interface level. 0 n 0 Notes: 1. I = Input, O = Output, P = Power supply connection, I PD = Input with pull down, I PU = Input with pull up. Pin Characteristics Symbol Parameter Conditions Min. Typ. Max. Units C Input Capacitance 4 pF IN R pullup Input Pullup Resistance 50 K R pulldown Input Pulldown Resistance 50 Control Input Function Table Inputs Outputs CLK EN CLK SEL Selected Source Q :Q Q : Q 0 3 n 0 n 3 0 0 CLK Diasbled: Low Diasbled: High 0 0 1 CLK Disabled: Low Disabled: High 1 1 0 CLK Enabled Enabled 0 1 1 CLK Enabled Enabled 1 Notes: 1. After CLK EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below. 2 PS8735A 03/25/11 11-0040