PI6C48535-11
3.3V Low Skew 1-to-4
Crystal/LVCMOS to LVPECL Fanout Buffer
Features Description
Maximum operation frequency: 500MHz
The PI6C48535-11 is a high-performance low-skew LVPECL
4 pair of differential LVPECL outputs fanout buffer. PI6C48535-11 features selectable of single-ended
clock or crystal inputs and translates to four LVPECL outputs.
Selectable CLK and crystal inputs
The CLK input accepts LVCMOS or LVTTL signals. The outputs
CLK accepts LVCMOS, LVTTL input level
are synchronized with input clock during asynchronous assertion
Output Skew: 30ps (maximum)
/deassertion of CLK_EN pin. PI6C48535-11 is ideal for crystal or
Part-to-part skew: 150ps (maximum) LVCMOS/LVTTL to LVPECL translation. Typical clock transla-
tion and distribution applications are data-communications and
Propagation delay: 1.5ns (maximum)
telecommunications.
3.3V power supply
Pin-to-pin compatible to ICS8535-11
o o
Operating Temperature: -40 C to 85 C
Packaging (Pb-free & Green available):
- 20-pin TSSOP (L)
Block Diagram
Pin Diagram
CLK_EN
D
V
EE 1 20 Q
0
Q
CLK_EN
2 19 Q
N 0
LE CLK_SEL
3 18 V
CC
CLK
4 17 Q
1
CLK NC
0 5 16 Q
N 1
Q
0
Xtal
1 6 15 Q
2
Q
n 0
Xtal1
1
Xtal
2 7 14 Q
N 2
Xtal2
Q
1 NC
8 13 V
CC
Q
n 1
NC
9 12 Q
3
V
CC 10 11 Q
N 3
Q
2
CLK_SEL
Q
n 2
Q
3
Q
n 3
PS9738A 10/13/08
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08-0257PI6C48535-11
3.3V Low Skew 1-to-4
Crystal/LVCMOS to LVPECL Fanout Buffer
Pin Description
Name Pin # Type Description
V 1 P Connect to Negative power supply
EE
Synchronizing clock enable. When high, clock outputs follow clock input. When low, Q
x
CLK_EN 2 I_PU outputs are forced low, Q outputs are forced high. LVCMOS/LVTTL level with 50K
n x
pull up.
Clock select input. When high, selects Xtal (Xtal1, Xtal2) inputs. When low, selects CLK
CLK_SEL 3 I_PD
input. LVCMOS/LVTTL level with 50K pull down.
CLK 4 I_PD LVCMOS / LVTTL clock input
Xtal1,
6, 7 Crystal input and output
Xtal2
NC 5, 8, 9 No internal connection.
10, 13,
V P Connect to 3.3V
CC
18
Q , Q 11, 12 O Differential output pair, LVPECL interface level.
3 n 3
Q , nQ2 14, 15 O Differential output pair, LVPECL interface level.
2
Q , Q 16, 17 O Differential output pair, LVPECL interface level.
1 n 1
Q , Q 19, 20 O Differential output pair, LVPECL interface level.
0 n 0
Notes:
1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up
Pin Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
C Input Capacitance 4 pF
IN
R_pullup Input Pullup Resistance 50 K
R_pulldown Input Pulldown Resistance 50 K
Control Input Function Table
Inputs Outputs
CLK_EN CLK_SEL Selected Source Q :Q Q : Q
03n 0 n 3
0 0 CLK Diasbled: Low Diasbled: High
0 1 Xtal1, Xtal2 Disabled: Low Disabled: High
1 0 CLK Enabled Enabled
1 1 Xtal1, Xtal2 Enabled Enabled
Notes:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.
PS9738A 10/13/08
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08-0257