VCCO VCCO
CLK1 VEE
/CLK1 VCC
SEL8 SEL11
SEL7 SEL10
SEL6
SEL9
SEL0
SEL3
SEL1 SEL4
SEL2
SEL5
CLK0
VCC
/CLK0
VEE
VCDD
VCCO
PI6C20800B
PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential
LVPECL Clock Multiplexer
Features Description
Pin-to-pin compatible to ICS85352I e PTh I6C485352 is a high-performance low-skew LVPECL
fanout buffer. PI6C485352 features two selectable differential
FMAX 500 MHz
inputs and translates to twelve LVPECL output pairs. The inputs
Propagation Delay < 4ns
can also be configured to single-ended with external resistor
Output-to-output skew < 100ps
bias circuit. The CLK input accepts LVPECL, LVDS, LVHSTL,
SSTL or HCSL signals. The PI6C485352 is ideal for differential
12 pairs of differential LVPECL outputs
to LVPECL translations and/or LVPECL clock distribution.
Selectable differential CLK and /CLK inputs
Typical clock translation and distribution applications are data-
CLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL and
communications and telecommunications.
HCSL input level
Applications
Select input accept CMOS/LVTTL levels
Networking systems including switches and Routers
2.5V/3.3V power supply
High frequency backplane based computing and telecom
Operating Temperature: -40C to +85C
platforms
Packaging (Pb-free & Green):
48-pin TQFP (FA)
Block Diagram Pin Configuration (48-Pin TQFP)
48 47 46 45 44 43 42 41 40 39 38 37
Q0 1 Q6
36
12
SEL [0:11]
/Q0 2 /Q6
35
Q1
3 Q7
34
CLK0 /Q1 4 /Q7
33
0
/CLK0
Q0
Q2 5 Q8
32
/Q0
/Q2
6 /Q8
CLK1 31
1
/CLK1
Q3 7 Q9
30
/Q3 8 /Q9
29
Q4 9 Q10
28
/Q4 10 /Q10
27
0
Q11 11
Q5 26 Q11
/Q11
12
/Q5 25
/Q11
1
13 14 15 16 17 18 19 20 21 22 23 24
PI6C485352 Rev. A 01/24/13
13-0003
1PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer
Pinout Table
Pin # Pin Name Type Description
1, 2 Q0, /Q0
3, 4 Q1, /Q1
5, 6 Q2, /Q2
7, 8 Q3, /Q3
9, 10 Q4, /Q4
11, 12 Q5, /Q5
Differential LVPECL Output pairs. LVPECL inter -
Output
face levels
25, 26 /Q11, Q11
27, 28 /Q10, Q10
29, 30 /Q9,Q9
31, 32 /Q8,Q8
33, 34 /Q7,Q7
35, 36 /Q6,Q6
13, 24
Output supply pins
V
CCO
37, 48
Power
14, 23 Ground pins
V
EE
15, 22 Core supply pins
V
CC
16, 17
SEL5, SEL4,
18, 19
SEL3, SEL9,
20, 21
SEL10, SEL11, Clock select inputs. LVCMOS/LVTTL interface
Pulldown
levels
40, 41
SEL8, SEL7,
42, 43 SEL6, SEL0,
44, 45 SEL1, SEL2
Pulldown
38 CLK1 Non-inverting differential clock input
39 /CLK1 Pullup/Pulldown Inverting differential clock input
46 CLK0 Pulldown Non-inverting differential clock input
47 /CLK0 Pullup/Pulldown Inverting differential clock input
PI6C485352 Rev. A 01/24/13
13-0003
2