PI6C48543 3.3V Low Skew 1-to-4, 800MHz, Differential to LVDS Fanout Buffer Features Description Maximum operation frequency: 800 MHz The PI6C48543 is a high-performance low-skew LVDS fanout 4 pair of differential LVDS outputs buffer. PI6C48543 features two selectable differential inputs and translates to four LVDS outputs. The inputs can also be con gured Selectable differential CLK and PCLK inputs to single-ended with external resistor bias circuit. The CLK input CLK, CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL n accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals, and HCSL input level and PCLK input accepts LVPECL or SSTL or CML signals. The PCLK, nPCLK pair supports LVPECL, CML and SSTL outputs are synchronized with input clock during asynchronous input level assertion/deassertion of CLK EN pin. PI6C48543 is ideal for Output Skew: 40ps (maximum) differential to LVDS translations and/or LVDS clock distribution. Typical clock translation and distribution applications are data- Part-to-part skew: 300ps (maximum) communications and telecommunications. Propagation delay: 2.2ns (maximum) 3.3V power supply Pin-to-pin compatible to ICS8543 o o Operating Temperature: -40 C to 85 C Packaging (Pb-free & Green): -20-pin TSSOP (L) Block Diagram Pin Diagram GND 1 20 Q 0 CLK EN D CLK EN 2 19 Q n 0 Q CLK SEL 3 18 V CC LE CLK 4 17 Q 1 CLK CLK n 5 16 Q n 1 0 CLK Q n 0 PCLK 6 15 Q 2 Q PCLK n 0 PCLK 7 n 14 Q n 2 1 PCLK n OE 8 13 GND Q 1 Q GND n 1 9 12 Q 3 V 10 CC 11 Q n 3 Q 2 CLK SEL Q n 2 Q 3 Q n 3 OE PS8771B 10/02/08 1 08-0247PI6C48543 3.3V Low Skew 1-to-4, 800MHz, Differential to LVDS Fanout Buffer Pin Description Name Pin Type Description GND 1, 9, 13 P Connect to Ground Synchronized clock enable. When high, clock outputs follow clock input. When low, Q x CLK EN 2 I PU outputs are forced low, Q outputs are forced high. LVCMOS/LVTTL level with 80k pull up. n x CLK Clock select input. When high, selects CLK input. When low, selects CLK input. LVCMOS/ 1 0 3 I PD SEL LVTTL level with 80k pull down. CLK 4 I PD Non-inverting differential clock input CLK 5 I PU Inverting differential clock input n PCLK 6 I PD Non-inverting differential clock input PCLK 7 I PU Inverting differential clock input n OE 8 I PU Output Enable, Controls outputs Q , Q through Q , Q 0 n 0 3 n 3 V 10, 18 P Connect to 3.3V. CC Q , Q 11, 12 O Differential output pair, LVDS interface level. 3 n 3 Q , Q 14, 15 O Differential output pair, LVDS interface level. 2 n 2 Q , Q 16, 17 O Differential output pair, LVDS interface level. 1 n 1 Q , Q 19, 20 O Differential output pair, LVDS interface level. 0 n Notes: 1. I = Input, O = Output, P = Power supply connection, I PD = Input with pull down, I PU = Input with pull up Pin Characteristics Symbol Parameter Conditions Min. Typ. Max. Units C Input Capacitance 6 pF IN R pullup Input Pullup Resistance 80 k R pulldown Input Pulldown Resistance 80 Control Input Function Table Inputs Outputs OE CLK EN CLK SEL Selected Source Q :Q Q : Q 03n 0 n 3 1 0 0 CLK, CLK Diasbled: Low Diasbled: High n 1 0 1 PCLK, PCLK Disabled: Low Disabled: High n 1 1 0 CLK, CLK Enabled Enabled n 1 1 1 PCLK, PCLK Enabled Enabled n 0 x x Hi-Z Hi-Z Notes: 1. After CLK EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below. PS8771B 10/02/08 2 08-0247