PI6C48545 3.3V Low Skew 1-to-4 LVTTL/LVCMOS to LVDS Fanout Buffer Features Description Maximum operation frequency: 650 MHz The PI6C48545 is a high-performance low-skew LVDS fanout buffer. PI6C48545 features two selectable single-ended clock in- 4 pair of differential LVDS outputs puts and translate to four LVDS outputs. The CLK and CLK 0 1 Selectable CLK and CLK inputs 0 1 inputs accept LVCMOS or LVTTL signals. The outputs are CLK , CLK accept LVCMOS, LVTTL input level 0 1 synchronized with input clock during asynchronous assertion/ Output Skew: 40ps (maximum) deassertion of CLK EN pin. PI6C48545 is ideal for single-ended LVTTL/LVCMOS to LVDS translations. Typical clock transla- Part-to-part skew: 300ps (maximum) tion and distribution applications are data-communications and Propagation delay: 2.2ns (maximum) telecommunications. 3.3V power supply Pin-to-pin compatible to ICS8545 o o Operating Temperature: -40 C to 85 C Packaging (Pb-free & Green): - 20-pin TSSOP (L) Block Diagram Pin Diagram D CLK EN Q 1 Q GND 20 0 LE nQ CLK EN 2 19 0 V CLK SEL 3 18 CC CLK 0 0 4 Q Q CLK 17 1 0 0 Q n 0 nQ NC 5 16 1 CLK 1 1 Q CLK 6 15 2 1 Q 1 7 nQ NC 14 2 Q n 1 GND OE 8 13 Q GND 9 12 3 Q 2 CLK SEL 10 nQ Q V 11 3 n 2 CC Q 3 Q n 3 OE PS8770 06/23/05 1PI6C48545 3.3V Low Skew 1-to-4 LVTTL/LVCMOS to LVDS Fanout Buffer Pin Description Name Pin Type Description GND 1, 9, 13 P Connect to Ground Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx CLK EN 2 I PU outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 80k pull up. Clock select input. When high, selects CLK input. When low, selects CLK input. 1 0 CLK SEL 3 I PD LVCMOS/LVTTL level with 80k pull down. CLK 4 I PD LVCMOS / LVTTL clock input 0 CLK 6 I PD LVCMOS / LVTTL clock input 1 NC 5, 7 No internal connection. OE 8 I PU Output Enable. Controls outputs Q , Q through Q , nQ 0 n 0 3 3. V 10, 18 P Connect to 3.3V. CC Q , Q 11, 12 O Differential output pair, LVDS interface level. 3 n 3 Q , Q 14, 15 O Differential output pair, LVDS interface level. 2 n 2 Q , Q 16, 17 O Differential output pair, LVDS interface level. 1 n 1 Q , Q 19, 20 O Differential output pair, LVDS interface level. 0 n 0 Notes: 1. I = Input, O = Output, P = Power supply connection, I PD = Input with pull down, I PU = Input with pull up. Pin Characteristics Symbol Parameter Conditions Min. Typ. Max. Units C Input Capacitance 6 pF IN R pullup Input Pullup Resistance 80 k R pulldown Input Pulldown Resistance 80 Control Input Function Table Inputs Outputs OE CLK EN CLK SEL Selected Source Q :Q Q : Q 0 3 n 0 n 3 1 0 0 CLK Diasbled: Low Diasbled: High 0 1 0 1 CLK Disabled: Low Disabled: High 1 1 1 0 CLK Enabled Enabled 0 1 1 1 CLK Enabled Enabled 1 0 x x HiZ HiZ Notes: 1. After CLK EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below. 2 PS8770 06/23/05