PI6C20800B PI6C4911504-03 High Performance LVPECL Fanout Buffer Features Description 4 LVPECL outputs e PTh I6C4911504-03 is a high performance fanout buffer device which supports up to 1.5GHz frequency. PI6C4911504-03 fea- Up to 1.5GHz output frequency tures selectable single-ended clock or crystal inputs and trans- Ultra low additive phase jitter: < 0.03 ps (typ) (differential lates to four LVPECL outputs. The outputs are synchronized 156.25MHz, 12KHz to 20MHz integration range) with input clock during asynchronous assertion /deassertion of Two selectable inputs CLK EN pin. PI6C4911504-03 is ideal for crystal or LVCMOS/ LVTTL to LVPECL translation. Typical clock translation and Low delay from input to output (Tpd typ. 1.5ns) distribution applications are data-communications and telecom- 2.5V / 3.3V power supply munications.This device is ideal for systems that need to distrib - Industrial temperature support ute low jitter clock signals to multiple destinations. TSSOP-20 package Applications Networking systems including switches and Routers High frequency backplane based computing and telecom platforms Block Diagram Pin Configuration (20-Pin TSSOP) V 20 EE 1 Q0 19 Q0 CLK EN 2 N CLK SEL 3 18 V CC CLK 4 17 Q1 16 Q1 NC 5 N Xtal 15 1 6 Q2 14 Xtal 7 Q2 2 N 13 NC 8 V CC 12 NC 9 Q3 11 V 10 Q3 CC N PI6C4911504-03 Rev. B 06/24/2013 13-0104 1PI6C4911504-03 High Performance LVPECL Fanout Buffer Pinout Table Pin Pin Name Type Description 1 V Power Negative power supply EE 2 CLK EN Input Pullup Clock output enable/ disable 3 CLK SEL Input Pulldown Clock input source selection pin 4 CLK Input Pulldown Clock input 5 NC - No Connect 6 XTAL1 Input Xtal input 7 XTAL2 Output Xtal output 8, 9 NC - No connect 10, 13, 18 V Power Power supply CC nQ3 11, 12 Output LVPECL output clock Q3 nQ2 14, 15 Output LVPECL output clock Q2 nQ1 16, 17 Output LVPECL output clock Q1 nQ0 19, 20 Output LVPECL output clock Q0 Note: Pullup and Pulldown are for internal input resistors Function Table Table 1: Clock source input select function CLK SEL Function 0 CLK is the selected reference input 1 XTAL is the selected input Table 2: Clock output select function CLK EN Function 0 All outputs disabled. Qx disabled low, nQx disabled High. 1 All outputs enabled. PI6C4911504-03 Rev. B 06/24/2013 13-0104 2