PI6C20800B PI6C4911505-07 High Performance 1:5 LVPECL Fanout Buffer Features Description 5 LVPECL outputs e PTh I6C4911505-07 is a high performance fanout buffer device - which supports up to 1.5GHz frequency. The device has 2 select - Up to 1.5GHz output frequency able clock inputs that can accept most differential clock sources. Ultra low additive phase jitter: < 0.03 ps (typ) (differential This device is ideal for systems that need to distribute low jitter 156.25MHz, 12KHz to 20MHz integration range) clock signals to multiple destinations. Two selectable inputs Low delay from input to output (Tpd typ. 1.5ns) Applications Separate Input output supply voltage for level shifting Networking systems including switches and Routers 2.5V / 3.3V power supply High frequency backplane based computing and telecom Industrial temperature support platforms TSSOP-20 package Block Diagram Pin Configuration (20-Pin TSSOP) Pulldown nEN D Q Q0 20 1 V DD LE Pulldown 19 nEN nQ0 2 CLK0 Pullup/Pulldown 0 Q 0 nCLK0 Q1 3 18 V Pulldown nQ0 DD CLK1 1 Pullup/Pulldown nCLK1 Q1 17 nQ1 4 nCLK1 Q n 1 16 CLK1 Q2 5 Q Pulldown 2 CLK SEL nQ2 nQ2 15 6 NC Q3 14 Q3 7 nCLK0 Q n 3 nQ3 8 13 CLK0 Q 4 Q n 4 12 Q4 9 CLK SEL 11 nQ4 10 V EE www.pericom.com PI6C4911505-07 Rev A 09/24/12 1 12-0265PI6C4911505-07 High Performance 1:5 LVPECL Fanout Buffer Pinout Table Pin Pin Name Type Description Q0 1, 2 Output LVPECL output clock nQ0 Q1 3, 4 Output LVPECL output clock nQ1 Q2 5, 6 Output LVPECL output clock nQ2 Q3 7, 8 Output LVPECL output clock nQ3 Q4 9, 10 Output LVPECL output clock nQ4 11 V Power Negative power supply EE 12 CLK SEL Input Clock input source selection pin CLK0 13, 14 Input Differential clock input nCLK0 15 NC - No Connect CLK1 16, 17 Input Differential clock input nCLK1 18, 20 V Power Power supply DD Synchronizing clock enable. When LOW, clock 19 nEN Input outputs enabled. When HIGH, Q outputs are forced low, nQ outputs forced high. www.pericom.com PI6C4911505-07 Rev A 09/24/12 2 12-0265