PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux Features Description F < 1.5GHz e PTh I6C4911510 is a high-performance low-skew 1-to-10 LVPECL MAX fanout buffer. The PI6C4911510 features two selectable dif - 10 pairs of differential LVPECL outputs ferential clock inputs and translates to ten LVPECL outputs. Low additive jitter, < 0.03ps (typ) e CTh LK inputs accept LVPECL, LVDS, CML and SSTL signals. Selectable differential input pairs with single ended input PI6C4911510 is ideal for clock distribution applications such as option providing fanout for low noise SaRonix-eCera oscillators. Input CLK accepts: LVPECL, LVDS, CML, SSTL input level Output skew: 40ps (typ) o o Operating Temperature: -40 C to 85 C Core Power supply: 2.5V 5% & 3.3V 10%, Output Power supply: 2.5V 5% & 3.3V 10% Packaging (Pb-free & Green): 32-pin QFN and TQFP available Block Diagram Pin Configuration 24 23 22 21 20 19 18 17 V v DDO 25 16 DDO /Q2 Q7 15 26 Q2 14 /Q7 27 /Q1 Q8 28 13 Q1 12 /Q8 29 /Q0 Q9 30 11 Q0 10 /Q9 31 v v DDO 32 9 DDO 1 2 3 4 5 6 7 8 PI6C4911510 Rev H 6/25/2015 1 15-0077 V DD Q3 CLK SEL /Q3 CLK0 Q4 /CLK0 /Q4 V (NC) BB Q5 CLK1 /Q5 /CLK1 Q6 V EE /Q6 PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux (1) Pin Description Pin Name Type Description 1 V Power Core Power Supply DD Clock select input. When high, selects CLK1 input. When low, selects CLK0 input. 2 CLK SEL Input LVCMOS/LVTTL level with 50k pull down. 3 CLK0 Input Differential clock input with pull-down 4 /CLK0 Input Inverting differential clock input. Defaults to V /2 if left floating. DD 5 V (NC) Power Internal Common Mode Voltage, can be left as not connected if unused. BB 6 CLK1 Input Differential clock input with pull-down 7 /CLK1 Input Inverting differential clock input. Defaults to V /2 if left floating. DD 8 V Power Connect to negative power supply EE 9, 16, 25, 32 V Power Output Power pin DDO Q9 Output Differential output pair, LVPECL interface level. 11, 10 Q9, / 13,12 Q8, Q8 Output Differential output pair, LVPECL interface level. / 15,14 Q7, Q7 Output Differential output pair, LVPECL interface level. / 18,17 Q6, Q6 Output Differential output pair, LVPECL interface level. / 20,19 Q5, Q5 Output Differential output pair, LVPECL interface level. / 22,21 Q4, Q4 Output Differential output pair, LVPECL interface level. / 24, 23 Q3, Q3 Output Differential output pair, LVPECL interface level. / 27,26 Q2, Q2 Output Differential output pair, LVPECL interface level. / 29,28 Q1, Q1 Output Differential output pair, LVPECL interface level. / 31,30 Q0, Q0 Output Differential output pair, LVPECL interface level. / Note: 1. I = Input, O = Output, P = Power supply connection. Control Input Function Table CLK SEL Outputs 0 CLK0 1 CLK1 2 PI6C4911510 Rev H 6/25/2015 15-0077