PI6C20800B PI6C4921506 High Performance LVDS Fanout Buffer Features Description 6 LVDS outputs e PTh I6C4921506 is a high performance fanout buffer device - which supports up to 1.5GHz frequency. The device also uses Up to 1.5GHz output frequency Pericom s proprietary input detection technique to make sure Ultra low additive phase jitter: < 0.03 ps (typ) (differential illegal input conditions will be detected and reefl cted by output 156.25MHz, 12KHz to 20MHz integration range) states. This device is ideal for systems that need to distribute low Single differential input jitter clock signals to multiple destinations. Low delay from input to output (Tpd typ. < 1.5ns) Separate Input output supply voltage for level shifting Applications 2.5V / 3.3V power supply Networking systems including switches and Routers Industrial temperature support High frequency backplane based computing and telecom TSSOP-24 package platforms Block Diagram Pin Configuration (24-Pin TSSOP) nCLK 24 GND 1 CLK 23 GND 2 VDD 22 3 VDD 21 VDDO 4 VDDO Q0 5 20 nQ5 nQ0 6 19 Q5 18 GND 7 GND 17 Q1 8 nQ4 nQ1 9 16 Q4 15 VDDO 10 VDDO 14 Q2 11 nQ3 12 13 Q3 nQ2 www.pericom.com Rev B 06/18/15 15-0080 1PI6C4921506 High Performance LVDS Fanout Buffer Pinout Table Pin Pin Name Type Description nCLK 1, 2 Input Differential clock input CLK 3, 22 V Power Power supply DD 4, 10, 15, 21 V Power IO power supply DDO Q0 5, 6 Output LVDS output clock nQ0 7, 18, 23, 24 GND Power Ground Q1 8, 9 Output LVDS output clock nQ1 Q2 11, 12 Output LVDS output clock nQ2 Q3 13, 14 Output LVDS output clock nQ3 Q4 16, 17 Output LVDS output clock nQ4 Q5 19, 20 Output LVDS output clock nQ5 Clock Input Function Table Inputs Outputs Input to Output Mode Polarity CLK nCLK Q0:Q5 nQ0:nQ5 0 1 LOW HIGH Differential to Differential Non Inverting 1 0 HIGH LOW Differential to Differential Non Inverting 0 Biased LOW HIGH Single Ended to Differential Non Inverting 1 Biased HIGH LOW Single Endded to Differential Non Inverting Biased 0 HIGH LOW Single Endded to Differential Inverting Biased 1 LOW HIGH Single Endded to Differential Inverting www.pericom.com Rev B 06/18/15 15-0080 2