PI6C49S1510 High Performance Differential Fanout Buffer Features Description 10 differential outputs with 2 banks e PTh I6C49S1510 is a high performance fanout buffer device - which supports up to 1.5GHz frequency. It also integrates a User configurable output signaling standard for each bank: unique feature with user configurable output signaling stan - LVDS or LVPECL or HCSL dards on per bank basis which provide great flexibilities to LVCMOS reference output up to 200MHz users. The device also uses Pericom s proprietary input detection Up to 1.5GHz output frequency for differential outputs technique to make sure illegal input conditions will be detected and reefl cted by output states. This device is ideal for systems Ultra low additive phase jitter: < 0.03 ps (typ) (differential that need to distribute low jitter clock signals to multiple desti- 156.25MHz, 12KHz to 20MHz integration range) < 0.02 ps nations. (typ) (differential 156.25MHz, 10kHz to 1MHz integration range) Selectable reference inputs support either single-ended Applications or differential or Xtal Networking systems including switches and Routers Low skew between outputs within banks (<40ps) High frequency backplane based computing and telecom Low delay from input to output (Tpd typ. < 1.7ns) platforms Separate Input output supply voltage for level shifting 2.5V / 3.3V power supply Industrial temperature support TQFN-48 package Block Diagram Pin Configuration (48-Pin TQFN) OPMODEA 1:0 48 47 46 45 44 43 42 41 40 39 38 37 QA 0:4 QAO+ 1 36 QBO+ 5 2 QAO- 35 QBO- QA1+ 3 34 QB1+ X1 OSC X2 QA1- 4 33 OPMODEB 1:0 QB1- IN0+ 5 IN0- V 32 V DDO QB 0:4 DDO 5 QA2+ 6 31 QB2+ IN1+ QA2- 7 30 IN1- QB2- Ref Out 8 V 29 DDO V DDO QA3+ 9 28 QB3+ IN SEL 1:0 QA3- 10 27 QB3- Sync OE Sync QA4+ 11 26 Iref QB4+ QA4- 12 25 QB4- 13 14 15 16 17 18 19 20 21 22 23 24 www.diodes.com August 2016 PI6C49S1510 Rev J 16-0147 1 Diodes Incorporated GND GND OPMODEA 1 OPMODEA 0 Sync OE V DD V X1 DDO Ref Out X2 GND GND V IN SEL 0 DD IN1+ IN0+ IN0- IN1- OPMODEB 1 IN SEL 1 Iref OPMODEB 0 GND GNDPI6C49S1510 Pinout Table Pin Pin Name Type Description QA0+ Bank A differential output pair 0. Pin selectable 1,2 Output LVPECL/LVDS/HCSL interface levels. QA0- QA1+ Bank A differential output pair 1. Pin selectable 3,4 Output LVPECL/LVDS/HCSL interface levels. QA1- 5,8,29,32,45 VDDO Power Power supply pins for IO QA2+ Bank A differential output pair 2. Pin selectable 6,7 Output LVPECL/LVDS/HCSL interface levels. QA2- QA3+ Bank A differential output pair 3. Pin selectable 9,10 Output LVPECL/LVDS/HCSL interface levels. QA3- QA4+ Bank A differential output pair 4. Pin selectable 11,12 Output LVPECL/LVDS/HCSL interface levels. QA4- 13,18,24,37,43,48 GND Power Power supply ground Output mode select for Bank A. See Table 2 for func- 14,47 OPMODEA Input Pulldown tions, LVCMOS/LVTTL interface levels 15,42 Power Power supply pins V DD XTAL input, can also be used as single ended input 16 X1 Input pin XTAL output. If X1 is used as a single ended input 17 X2 Output pin, X2 is to be left open Input clock sele ct. See Table 1 for function. LVC- 19,22 IN SEL Input Pulldown MOS/LVTTL interface levels. 20 IN0+ Input Pulldown Reference input 0 Pull-up/ 21 IN0- Input Inverted reference input 0, internal bias to V DD/2 Pulldown Output mode select for Bank B. See Table 2for func- 23,39 OPMODEB Input Pulldown tions, LVCMOS/LVTTL interface levels QB4+ Bank B differential output pair 4. Pin selectable 26,25 Output LVPECL/LVDS/HCSL interface levels. QB4- QB3+ Bank B differential output pair 3. Pin selectable 28,27 Output LVPECL/LVDS/HCSL interface levels. QB3- QB2+ Bank B differential output pair 2. Pin selectable 31,30 Output LVPECL/LVDS/HCSL interface levels. QB2- QB1+ Bank B differential output pair 1. Pin selectable 34,33 Output LVPECL/LVDS/HCSL interface levels. QB1- www.diodes.com August 2016 PI6C49S1510 Rev J 16-0147 2 Diodes Incorporated