PI6C557-06 1:4 HCSL PCIe Buffer Features Description 1:4 HCSL clock buffer e Th PI6C557-06 is a high performance PCIe buffer with four HCSL outputs compliant to PCIe Gen 1, 2 and 3 standards. e Th PCIe Gen 1, 2 and 3 compliant device has selectable reference inputs to provide efl xibility in sys - Selectable reference inputs tem design. Cycle-to-Cycle Jitter <70ps Output-to-Output Skew <35ps 3.3V supply voltage TSSOP-20 package Industrial Temperature Applications Servers Embedded computing systems Networking systems Block Diagram Pin Configuration 1 OE REFSEL 20 CLK0 CLK0 CLK0 2 VDDIN 19 CLK0 CLK1 3 SRCIN1 18 CLK1 SRCIN1 CLK1 4 SRCIN1 SRCIN1 17 CLK1 CLK2 CLK2 PD 5 16 GND SRCIN2 SRCIN2 6 SRCIN2 15 VDDOUT CLK3 CLK3 SRCIN2 7 14 CLK2 REFSEL 8 OE 13 CLK2 GND 9 12 CLK3 PD 10 IRef 11 CLK3 All trademarks are property of their respective owners. www.pericom.com P-0.1 09/15/10 11-0051 1PI6C557-06 1:4 HCSL PCIe Buffer Function Table REFSEL INPUT Selected 0 SRCIN2 / SRCIN2 1 SRCIN1 / SRCIN1 Pin Description Pin Pin Type Description 1 REFSEL Input Internal pull up. 0 select SRCIN2/2 1 selects SRCIN1/1 . 2 VDDIN Power 3.3V for input buffer 3, 4 SRCIN1, SRCIN1 Input HCSL Input 1 Power Down mode. 0 is power down, 1 is normal operation. Internal pull 5 PD Input up. Outputs are in tri-state when power down. 6, 7 SRCIN2, SRCIN2 Input HCSL input 2 Output enable for all outputs. 0 is disabled as tri-stated, 1 is enable ou- t 8 OE Input put mode. Internal pull up. 9,16 GND Power Ground 10 IRef Input External resistor connection for internal current reference 11,12 CKL3 , CLK3 Output HCSL output 13,14 CKL2 , CLK2 Output HCSL output 15 VDDOUT Power 3.3V for outputs 17, 18 CKL1 , CLK1 Output HCSL output 19, 20 CKL0 , CLK0 Output HCSL output All trademarks are property of their respective owners. www.pericom.com P-0.1 09/15/10 11-0051 2