A product Line of Diodes Incorporated PI6CB18200 Very Low Power 2-Output PCIe Clock Buffer Features Description 1.8V supply voltage e PTh I6CB18200 is an 2-output very low power PCIe Gen1/ HCSL input: 100MHz, also suppport 50MHz or 125MHz via Gen2/Gen3/ Gen4 clock buffer. It takes an reference input to SMBus fanout two 100MHz low power differential HCSL outputs. 2 differential low power HCSL outputs Individual OE pin for each output provides easier power man- agement. Individual output enable Programmable Slew rate and output amplitute for each It uses Diodes proprietary PLL design to achieve very low jitter output that meets PCIe Gen1/Gen2/Gen3 requirements. Other than Differential outputs blocked until PLL is locked PCIe 100MHz support, this device also support Ethernet Strapping pins or SMBus for configuration application with 50MHz or 125MHz via SMBus. It provides various options such as different slew rate and amplitude 3.3V tolerant SMBus interface support through strapping pins or SMBUS so that users can configure Very low jitter outputs the device easily to get the optimized performance for their Differential cycle-to-cycle jitter <50ps individual boards. Differential output-to-output skew <50ps PCIe Gen1/Gen2/Gen3/ Gen4 compliant Packaging (Pb-free & Green): 24-lead 44mm TQFN Pin Configuration 24 23 22 21 20 19 1 Q1- NC 18 V DD R 2 17 Q1+ 3 IN+ 16 VDDA GND 4 GNDA IN- 15 Q0- GND R 5 14 Q0+ GND DIG 6 13 7 8 9 10 11 12 www.diodes.com September 2017 PI6CB18200 1 Diodes Incorporated Document Number DS40224 Rev 2-2 V DD DIG NC SCLK BW SEL TRI SDATA PD GND GND V V DDO DDO OE0 OE1 A product Line of Diodes Incorporated PI6CB18200 Block Diagram OE 1:0 Q1 IN+ PLL IN- Q0 SCLK SDATA SADR TRI CTRL BW SEL TRI LOGIC PD Pin Description Pin Number Pin Name Type Description 1, 24 NC Internal connected for feedback loop. Do not connect this pin 2 V R Power Power supply for input differential buffers DD 3 IN+ Input Differential true clock input 4 IN- Input Differential complementary clock input 5 GND R Power Ground for input differential buffers 6 GND DIG Power Ground for digital circuitry 7 V DIG Power Power supply for digital circuitry, nominal 1.8V DD 8 SCLK Input CMOS SMBUS clock input, 3.3V tolerant Input/ 9 SDATA CMOS SMBUS Data line, 3.3V tolerant Output 10, 21 GND Power Ground 11, 20 V Power Power supply for differential outputs DDO Active low input for enabling Q0 pair. This pin has an internal pull-down. 12 OE0 Input CMOS 1 =disable outputs, 0 = enable outputs 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output 15 GNDA Power Ground for analog circuitry 16 V Power Power supply for analog circuitry DDA 17 Q1+ Output HCSL Differential true clock output 18 Q1- Output HCSL Differential complementary clock output Active low input for enabling Q1 pair. This pin has an internal pull-down. 19 OE1 Input CMOS 1 =disable outputs, 0 = enable outputs Input notifies device to sample latched inputs and start up on first high 22 PD Input CMOS assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. Latch to select low loop bandwidth, bypass PLL, and high loop band- 23 BW SEL TRI Input Tri-level width. This pin has both internal pull-up and pull-down www.diodes.com September 2017 PI6CB18200 2 Diodes Incorporated Document Number DS40224 Rev 2-2