A product Line of Diodes Incorporated PI6CB18401 Very Low Power 4-Output PCIe Clock Buffer With On-chip Termination Features Description 1.8V supply voltage e PTh I6CB18401 is an 4-output very low power PCIe Gen1/Gen2/ Gen3/Gen4 clock buffer. It takes an reference input to fanout four HCSL input: 100MHz, also suppport 50MHz or 125MHz via 100MHz low power differential HCSL outputs with on-chip ter - SMBus minations. The on-chip termination can save 16 external resistors 4 differential low power HCSL outputs with on-chip and make layout easier. Individual OE pin for each output pro- termination vides easier power management. Individual output enable Programmable Slew rate and output amplitute for each It uses Pericom proprietary PLL design to achieve very low jit- output ter that meets PCIe Gen1/Gen2/Gen3/Gen4 requirements. Other than PCIe 100MHz support, this device also support Ethernet ap- Differential outputs blocked until PLL is locked plication with 50MHz or 125MHz via SMBus. It provides various Strapping pins or SMBus for configuration options such as different slew rate and amplitude through strap - 3.3V tolerant SMBus interface support ping pins or SMBUS so that users can configure the device easily Very low jitter outputs to get the optimized performance for their individual boards. yDifferential cycle-to-cycle jitter <50ps yDifferential output-to-output skew <50ps yPCIe Gen1/Gen2/Gen3/Gen4 compliant Packaging (Pb-free & Green): 32-lead 55mm TQFN Block Diagram OE 3:0 Q3 Q2 IN+ PLL IN- Q1 Q0 SCLK SDATA SADR TRI CTRL BW SEL TRI LOGIC PD www.diodes.com January 2018 PI6CB18401 Diodes Incorporated Document Number DS40617 Rev 1-2 1A product Line of Diodes Incorporated PI6CB18401 Pin Configuration 32 31 30 29 28 27 26 25 BW SEL TRI 1 24 OE2 Q2- NC 2 23 NC 3 Q2+ 22 V DD R 4 21 VDDA GND IN+ 5 20 GNDA Q1- IN- 6 19 Q1+ GND R 7 18 GND DIG 8 OE1 17 9 10 11 12 13 14 15 16 Pin Description Pin Number Pin Name Type Description Latch to select low loop bandwidth, bypass PLL, and high loop band- 1 BW SEL TRI Input Tri-level width. This pin has both internal pull-up and pull-down 2 NC Internal connected for feedback loop. Do not connect this pin 3 NC Internal connected for feedback loop. Do not connect this pin 4 V R Power Power supply for input differential buffers DD 5 IN+ Input Differential true clock input 6 IN- Input Differential complementary clock input 7 GND R Power Ground for input differential buffers 8 GND DIG Power Ground for digital circuitry 9 V DIG Power Power supply for digital circuitry, nominal 1.8V DD 10 SCLK Input CMOS SMBUS clock input, 3.3V tolerant Input/ 11 SDATA CMOS SMBUS Data line, 3.3V tolerant Output Active low input for enabling Q0 pair. This pin has an internal pull-down. 12 OE0 Input CMOS 1 =disable outputs, 0 = enable outputs 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output 15, 26, 30 GND Power Ground 16, 25 V Power Power supply for differential outputs DDO Active low input for enabling Q1 pair. This pin has an internal pull-down. 17 OE1 Input CMOS 1 =disable outputs, 0 = enable outputs www.diodes.com January 2018 PI6CB18401 2 Diodes Incorporated Document Number DS40617 Rev 1-2 V DD DIG SADR TRI PD SCLK SDATA GND OE0 OE3 Q0+ Q3- Q0- Q3+ GND GND V V DDO DDO