A product Line of Pb Diodes Incorporated Lead-free Green PI6CB33202 Very-Low-Power Two-Output PCIe Clock Buffer With On-Chip Termination Features Description 3.3V Supply Voltage e PTh I6CB33202 is a two-output very-low-power PCIe Gen1/ Gen2/Gen3/Gen4/Gen5 clock buffer. It takes a reference input to HCSL Input: 100MHz Also supports 50MHz, 125MHz, or fan out two 100MHz low-power differential HCSL outputs with 133.33MHz via SMBus on-chip terminations. The on-chip termination can save eight Two Differential Low-Power HCSL Outputs with On-Chip external resistors and make layout easier. Individual OE pin for Termination each output provides easier power management. Default Z = 85 OUT Spread Spectrum Tolerant It uses Diodes proprietary PLL design to achieve very-low jitter that meets PCIe Gen1/Gen2/Gen3/Gen4/Gen5 requirements. Individual Output Enable Other than PCIe 100MHz support, this device also support Eth- Programmable Slew Rate and Output Amplitude for Each ernet application with 50MHz, 125MHz, and 133.33MHz via Output SMBus. It provides various options such as different slew rate Differential Outputs Blocked until PLL is Locked and amplitude through SMBUS, so users can configure the de - Strapping Pins or SMBus for Configuration vice easily to get the optimized performance for their individual boards. Differential output-to-output skew <50ps Very low jitter outputs Differential cycle-to-cycle jitter <50ps Block Diagram PCIe Gen1/Gen2/Gen3/Gen4/Gen5 CC compliant PCIe Gen 2 and 3 SRiS and SRnS compliant OE 1:0 Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Q1 IN+ PLL Halogen and Antimony Free. Green Device (Note 3) IN- Q0 For automotive applications requiring specic cfi hange control (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, SCLK and manufactured in IATF 16949 certified facilities), please SDATA contact us or your local Diodes representative. SADR TRI CTRL BW SEL TRI LOGIC A product Line of Diodes Incorporated PI6CB33202 Pin Configuration OE 3:0 Q3 Q2 IN+ PLL IN- 24 23 22 21 20 19 Q1 NC 1 18 Q1- Q1+ NC 2 17 Q0 SCLKV 3 16 VDDA DD R SDATA IN+ SADR TRI 4 15 OE0 CTRL BW SEL TRI GND LOGIC IN- 5 14 Q0- PD GND DIG 6 13 Q0+ 7 8 9 10 11 12 Pin Description Pin Number Pin Name Type Description 1 NC Internal connected for feedback loop. Do not connect this pin. 2 NC Internal connected for feedback loop. Do not connect this pin. 3 V R Power Power supply for input differential buffers DD 4 IN+ Input Differential true clock input 5 IN- Input Differential complementary clock input 6 GND DIG Power Ground for digital circuitry Input/ 7 SDATA CMOS SMBUS data line, 3.3V tolerant Output 8 V DIG Power Power supply for digital circuitry, nominal 3.3V DD 9 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 10 V Power Power supply for differential outputs DDO 11 NC Do not connect this pin. 12 NC Do not connect this pin. 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output Active-low input for enabling Q0 pair. This pin has an internal pulldown. 15 OE0 Input CMOS 1 =disable outputs, 0 = enable outputs 16 V Power Power supply for analog circuitry DDA 17 Q1+ Output HCSL Differential true clock output www.diodes.com March 2020 PI6CB33202 22 Diodes Incorporated Document Number DS41834 Rev 6-2 SDATA BW SEL TRI V DIG SADR TRI DD SCLK PD V O DD VDDO NC NC OE1 NC